Circuit device, oscillator, electronic apparatus, and vehicle

Patent metadata

Field	Value
Publication number	US-2017194966-A1
Application number	US-201615384885-A
Country	US
Kind code	A1
Filing date	Dec 20, 2016
Priority date	Jan 6, 2016
Publication date	Jul 6, 2017
Grant date	—

Abstract

A circuit device includes a digital interface, a processor, an oscillation signal generation circuit, a clock signal generation circuit that generates a clock signal having frequency obtained through multiplication of a frequency of the oscillation signal, and terminal groups of the digital interface and the clock signal generation circuit. The terminal group of the digital interface is disposed in a first region along a first side of the circuit device, and the terminal group of the clock signal generation circuit is disposed in any one of second, third and fourth regions of the circuit device.

First claim

What is claimed is:

1 . A circuit device comprising:
a digital interface; a processor that is connected to the digital interface; an oscillation signal generation circuit that generates an oscillation signal by using data from the processor and a resonator; a clock signal generation circuit that generates a clock signal having a frequency which is obtained through multiplication of an oscillation frequency of the oscillation signal; a terminal group of the digital interface, disposed in a first region along a first side of the circuit device; and a terminal group of the clock signal generation circuit, disposed in any one of a second region along a second side of the circuit device that intersects the first side, a third region along a third side of the circuit device that opposes the first side, and a fourth region along a fourth side of the circuit device that opposes the second side.

2 . The circuit device according to claim 1 , further comprising:
a terminal group of the oscillation signal generation circuit, disposed in the second region.

3 . The circuit device according to claim 2 ,
wherein the terminal group of the clock signal generation circuit is disposed in the third region.

4 . The circuit device according to claim 1 ,
wherein the first side is a short side of the circuit device.

5 . The circuit device according to claim 2 ,
wherein, at least one of a distance L 12 between the terminal group of the digital interface and the terminal group of the oscillation signal generation circuit and a distance L 13 between the terminal group of the digital interface and the terminal group the clock signal generation circuit, is longer than a distance L 23 between the terminal group of the oscillation signal generation circuit and the terminal group of the clock signal generation circuit.

6 . The circuit device according to claim 1 ,
wherein frequency control data from an external device is input to the processor via the terminal group for connection of the digital interface, and the digital interface, the external device being a device that compares an input signal based on the oscillation signal with a reference signal, wherein the processor is configured to perform a signal process on the frequency control data to output processed frequency control data, and wherein the oscillation signal generation circuit generates the oscillation signal on the basis of the processed frequency control data.

7 . The circuit device according to claim 6 , further comprising:
a phase comparator that compares a phase of an input signal based on the oscillation signal with a phase of the reference signal, wherein the oscillation signal generation circuit generates the oscillation signal on the basis of the frequency control data from the external device in a first mode, and generates the oscillation signal on the basis of the frequency control data from the phase comparator in a second mode.

8 . The circuit device according to claim 1 ,
wherein the digital interface is a 2-wire, 3-wire, or 4-wire serial interface circuit including a serial data line and a serial clock line.

9 . The circuit device according to claim 1 ,
wherein the processor is disposed between the first region and the clock signal generation circuit.

10 . The circuit device according to claim 9 ,
wherein the oscillation circuit is disposed between the processor and the clock signal generation circuit.

11 . The circuit device according to claim 1 , further comprising:
a terminal group that is disposed in the fourth region and includes an oven control terminal of an oven type oscillator comprising the resonator and a thermostatic oven.

12 . The circuit device according to claim 11 , further comprising:
an oven control circuit that is connected to the oven control terminal and controls the oven of the oven type oscillator.

13 . The circuit device according to claim 12 ,
wherein the oscillation circuit is disposed between the oven control circuit and the second region.

14 . An oscillator comprising:
a resonator; and a circuit device including
a digital interface;
a processor that is connected to the digital interface;
an oscillation signal generation circuit that generates an oscillation signal by using data from the processor and a resonator;
a clock signal generation circuit that generates a clock signal having a frequency which is obtained through multiplication of an oscillation frequency of the oscillation signal;
a terminal group of the digital interface, disposed in a first region along a first side of the circuit device; and p 2 a terminal groupof the clock signal generation circuit, disposed in any one of a second region along a second side of the circuit device that intersects the first side, a third region along a third side of the circuit device that opposes the first side, and a fourth region along the fourth side of the circuit device that opposes the second side.

15 . An electronic apparatus comprising the circuit device according to claim

16 . A vehicle comprising the circuit device according to claim 1 .

Assignees

• Seiko Epson Corp

Inventors

• Yonezawa Takemi

Classifications

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/14

  for assuring constant frequency when supply or correction voltages fail · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title