Low temperature fabrication of lateral thin film varistor

Patent metadata

Field	Value
Publication number	US-10170224-B2
Application number	US-201715821433-A
Country	US
Kind code	B2
Filing date	Nov 22, 2017
Priority date	Feb 26, 2015
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may include a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.

First claim

What is claimed is:

1. A lateral thin film varistor device, comprising:
a substrate;
a dielectric layer on the substrate;
two electrodes on the dielectric layer and spaced apart from each other in a first, lateral direction; and
a continuous, varistor layer on the dielectric layer and located between, and in contact with, the two electrodes, and comprising regions of a first metal oxide layer, and regions of a second metal oxide layer, and wherein:
the regions of the first metal oxide layer alternate with the regions of the second metal oxide layer in the lateral direction between the two electrodes,
the regions of the second metal oxide layer project outside the regions of the first metal oxide layer in a second, transverse direction perpendicular to the lateral direction, and
two of the regions of the first metal oxide layer are located laterally outside the regions of the second metal oxide layer, in contact with the two electrodes.

2. The lateral thin film varistor device according to claim 1 , further comprising first and second conductive vias, each of the conductive vias being connected to a respective one of the electrodes.

3. The lateral thin film varistor device according to claim 2 , wherein the conductive vias are laterally outside of the continuous varistor layer.

4. The lateral thin film varistor device according to claim 1 , wherein the regions of the first metal oxide layer and the regions of the second metal oxide layer have substantially co-planar upper surfaces.

5. A lateral thin film varistor device according to claim 4 , wherein the two electrodes have upper surfaces substantially coplanar with the upper surfaces of the regions of the first and second meal oxide layers.

6. A lateral thin film varistor device according to claim 1 , wherein the first metal oxide layer is comprised of zinc oxide.

7. A lateral thin film varistor device according to claim 6 , wherein the second metal oxide layer is comprised of bismuth oxide.

8. A lateral thin film varistor device according to claim 7 , wherein the first metal oxide layer is doped with aluminum oxide, and the second metal oxide layer is doped with aluminum oxide.

9. A lateral thin film varistor device according to claim 1 , wherein the regions of the first metal oxide layer have a thickness between 50 nm and 500 nm.

10. A lateral thin film varistor device according to claim 9 , wherein the first metal oxide layer includes zinc crystal grains having a size between 10 nm and 300 nm.

11. A method of forming a lateral thin film varistor device, comprising:
forming a dielectric layer on a substrate:
forming a continuous, varistor layer on the dielectric layer, including
forming regions of a first metal oxide layer on the dielectric using a first sputtering process and a first annealing process,
forming regions of a second metal oxide layer on the dielectric using a second sputtering process and a second annealing process,
alternating the regions of the first metal oxide layer with the regions of the second metal oxide layer in a first, lateral direction,
projecting the regions of the second metal oxide layer outside the regions of the first metal oxide layer in a second, transverse direction perpendicular to the lateral direction, and
locating two of the regions of the first metal layer laterally outside the regions of the second metal oxide layer; and

forming two electrodes on the dielectric layer spaced apart and outside of the continuous, varistor layer, in the lateral direction, with said two regions of the first metal layer in contact with the two electrodes.

12. The method according to claim 11 , further comprising connecting a first conductive via to a first of the electrodes, and connecting a second conductive vias to a second of the electrodes.

13. The method according to claim 12 , wherein the conductive vias are laterally outside of the continuous, varistor layer.

14. The method according to claim 11 , wherein the regions of the first metal oxide layer and the regions of the second metal oxide layer have substantially co-planar upper surfaces.

15. The method according to claim 14 , wherein the forming two electrodes on the dielectric layer includes forming upper surfaces of the two electrodes substantially co-planar with the upper surfaces of the regions of the first and second metal oxide layers.

16. A method of forming a lateral thin film varistor device, comprising:
forming a dielectric layer on a substrate:
forming a continuous, varistor layer on the dielectric layer, including
forming regions of a zinc oxide layer on the dielectric using a first sputtering process and a first annealing process,
forming regions of a bismuth oxide layer on the dielectric using a second sputtering process and a second annealing process,
alternating the regions of the zinc oxide layer with the regions of the bismuth oxide layer in a first, lateral direction,
projecting the regions of the bismuth oxide layer outside the regions of the zinc oxide layer in a second, transverse direction perpendicular to the lateral direction, and
locating two of the regions of the zinc oxide layer laterally outside the regions of the bismuth oxide layer; and

forming two electrodes on the dielectric layer spaced apart and outside of, and in contact with, the continuous, varistor layer, in the lateral direction.

17. The method according to claim 16 , further comprising:
doping the zinc oxide layer with aluminum oxide; and
doping the bismuth oxide layer with aluminum oxide.

18. The method according to claim 16 , wherein the regions of the zinc oxide layer have a thickness between 50 nm and 500 nm.

19. The method according to claim 18 , wherein the zinc metal oxide layer includes zinc crystal grains having a size between 10 nm and 300 nm.

20. The method according to claim 16 , wherein the forming two electrodes on the dielectric layer includes forming the two electrodes outside of, and in contact with, the two regions of the zinc oxide layer.

Assignees

• IBM

Inventors

• Gambino Jeffrey P
• Graf Richard S
• Mandal Sudeep

Classifications

• H10P14/6939

  characterised by the metal · CPC title

• H10P14/6329

  using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title

• H10P14/662

  Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W44/401

  Resistive arrangements (H10W44/20, H10W42/80 take precedence) · CPC title