Secure off-chip MRAM

Patent metadata

Field	Value
Publication number	US-10170178-B2
Application number	US-201715590521-A
Country	US
Kind code	B2
Filing date	May 9, 2017
Priority date	May 9, 2017
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Techniques for improving the security of nonvolatile memory such as magnetic random access memory (MRAM) are provided. In one aspect, a method of operating a nonvolatile memory chip is provided. The method includes: overwriting data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on. For example, all bits in the nonvolatile memory chip can be written to either i) a predetermined data state (e.g., a logic 1 or a logic 0) or ii) a random data state. A system is also provided that includes: a nonvolatile memory chip; and a writing circuit configured to overwrite data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory chip, comprising the steps of:
overwriting data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on; and
providing a user with an option to change a security setting from a volatile mode whereby the data is overwritten automatically upon the nonvolatile memory chip being powered on to a nonvolatile mode whereby the overwriting step is bypassed.

2. The method of claim 1 , wherein the nonvolatile memory chip comprises a magnetic random access memory (MRAM) chip.

3. The method of claim 1 , wherein the step of overwriting comprises the step of:
writing all bits in the nonvolatile memory chip to either i) a predetermined data state or ii) a random data state.

4. The method of claim 3 , wherein the predetermined data state comprises either a logic 1 or a logic 0.

5. The method of claim 3 , wherein the bits comprise both data bits and error-correcting code (ECC) hits.

6. The method of claim 3 , wherein the overwriting step is completed only when all of the bits in the nonvolatile memory chip have been written.

7. The method of claim 6 , wherein the nonvolatile memory chip is powered off while the overwriting step is being performed, the method further comprising the step of:
restarting the overwriting step automatically when the nonvolatile memory chip is again powered on.

8. The method of claim 1 , further comprising the step of:
detecting that the nonvolatile memory chip has been powered on.

9. The method of claim 1 , further comprising the step of:
generating a clock signal upon the nonvolatile memory chip being powered on.

10. The method of claim 1 , wherein the user is provided with the option to change the security setting only after the overwriting step has been performed at least once.

11. The method of claim 1 , further comprising the step of:
storing the security setting as a flag in one or more bits in the nonvolatile memory chip.

12. The method of claim 11 , wherein the flag is stored in multiple bits in the nonvolatile memory chip.

13. The method of claim 12 , wherein the flag is stored in physically adjacent bits in the nonvolatile memory chip.

14. The method of claim 12 , wherein the multiple bits have different logic states depending on whether the security setting is in the volatile mode or in the nonvolatile mode.

15. A system, comprising:
a nonvolatile memory chip; and
a writing circuit configured to overwrite data stored on the nonvolatile memory chip automatically upon the nonvolatile memory chip being powered on, after which the nonvolatile memory chip will accept external commands including commands from a user to change a security setting from a volatile mode whereby the data is overwritten automatically upon the nonvolatile memory chip being powered on to a nonvolatile mode whereby overwriting the data is bypassed.

16. The system of claim 15 , wherein the nonvolatile memory chip comprises an MRAM chip.

17. The system of claim 15 , further comprising:
a power-on-detector (POD) circuit configured to generate a signal upon the nonvolatile memory chip being powered on.

18. The system of claim 17 , further comprising:
a clock generator circuit configured to generate a clock signal upon receipt of the signal from the POD circuit.

19. The system of claim 18 , wherein the writing circuit is configured to overwrite the data stored on the nonvolatile memory chip upon receipt of the clock signal from the clock signal generator.

Assignees

• IBM

Inventors

• Debrosse John K
• Hall William E
• Hunter Hillery C
• Stuecheli Jeffrey A
• Worledge Daniel C

Classifications

• G06F11/2215

  to test error correction or detection circuits · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C16/105 Primary

  Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written · CPC title

• G11C11/1695

  Protection circuits or methods · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title