Critical path delay prediction

Patent metadata

Field	Value
Publication number	US-10169500-B2
Application number	US-201113204812-A
Country	US
Kind code	B2
Filing date	Aug 8, 2011
Priority date	Aug 8, 2011
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.

First claim

What is claimed is:

1. A method of predicting a delay of one or more critical paths of an integrated circuit, the method comprising:
determining a respective delay of each of a plurality of on-board ring oscillators on the integrated circuit based on a real-time measurement of a respective frequency of each of the plurality of ring oscillators,
wherein the plurality of on-board ring oscillators includes one or more on-board high-voltage threshold (HVT) ring oscillators, one or more on-board medium-voltage threshold (SVT) ring oscillators, and one or more on-board low-voltage threshold (UVT) ring oscillators; and
calculating, using a computer system processor, a predicted delay for each of the one or more critical paths based on a delay of components of the respective critical path at a corner condition, a wire delay of the respective critical path, a delay of each of the plurality of on-board ring oscillators at a corner condition, and the determined delay of each of the plurality of on-board ring oscillators,
wherein each of the one or more critical paths include at least one HVT component on the integrated circuit having a first voltage threshold, at least one SVT component on the integrated circuit having a second voltage threshold less than the first voltage threshold, and at least one UVT component on the integrated circuit having a third voltage threshold less than both the first voltage threshold and the second voltage threshold.

2. The method of claim 1 ,
wherein calculating the predicted delay of each of the one or more critical paths includes calculating the predicted delay of each of the one or more critical paths according to the equation:

D
cp

=

(

[

D

HVTC
cc

×

{

D
HVTRO

D

HVTRO
cc

}

]

+

[

D

SVTC
cc

×

{

D
SVTRO

D

SVTRO
cc

}

]

+

[

D

UVTC
cc

×

{

D
UVTRO

D

UVTRO
cc

}

]

+

D
W

)

,

wherein D cp is the predicted delay of the respective critical path, D HVTC cc is the delay of HVT components of the respective critical path at a corner condition, D HVTRO is the determined delay of the HVT ring oscillators, D HVTR cc is the delay of the HVT ring oscillators at a corner condition, D SVTC cc is the delay of SVT components of the respective critical path at a corner condition, D SVTRO is the determined delay of the SVT ring oscillators, D SVTRO cc is the delay of the SVT ring oscillators at a corner condition, D UVTC cc is the delay of UVT components of the respective critical path at a corner condition, D UVTRO is the determined delay of the UVT ring oscillators, D UVTRO cc is the delay of the UVT ring oscillators at a corner condition, and D W is the wire delay of the respective critical path.

3. The method of claim 1 , further comprising:
adding to the predicted delay of each of the one or more critical paths at least one of the following: a timing margin or a technology margin.

4. The method of claim 1 , wherein the one or more critical paths includes a plurality of critical paths and the method further comprises determining a longest predicted critical path delay from among the plurality of predicted delays calculated for the plurality of critical paths.

5. The method of claim 4 , further comprising:
calculating a critical path slack according to the equation:

S
cp

=

(

1

F
sys

)

-

longest
⁢

⁢

D
cp

,

wherein S ep is the critical path slack, F sys is a system frequency, and longest D cp is the longest predicted critical path delay.

6. A system comprising:
at least one computing device configured for predicting a delay of one or more critical paths of an integrated circuit by performing a method comprising:
determining a respective delay of each of a plurality of on-board ring oscillators on the integrated circuit based on a real-time measurement of a respective frequency of each of the at least one plurality of ring oscillators,
wherein the plurality of on-board ri

Assignees

• Charlebois Margaret R
• Chatty Rashmi D
• Hanudel Christopher D
• Herzl Robert D
• Milton David W
• Ogilvie Clarence R
• Szafir Matthew P
• Wilder Tad J
• IBM

Inventors

• Charlebois Margaret R
• Chatty Rashmi D
• Hanudel Christopher D
• Herzl Robert D
• Milton David W
• Ogilvie Clarence R
• Szafir Matthew P
• Wilder Tad J

Classifications

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F17/5031 Primary

  Physics · mapped topic