Circuit for addition of multiple binary numbers

Patent metadata

Field	Value
Publication number	US-10168991-B2
Application number	US-201615381424-A
Country	US
Kind code	B2
Filing date	Dec 16, 2016
Priority date	Sep 26, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A circuit is provided for addition of multiple binary numbers. The circuit includes a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor. The 4-to-2-compressor includes a first sub-circuit and a second sub-circuit. Each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation, of a compressed representation, from three binary numbers.

First claim

What is claimed is:

1. A circuit for addition of multiple binary numbers, the circuit comprising a 4-to-2-compressor configured for calculating a compressed representation from four binary numbers received via operand inputs of the 4-to-2-compressor, wherein the 4-to-2-compressor comprises a first sub-circuit and a second sub-circuit, wherein each of the first sub-circuit and the second sub-circuit is configured for transmitting a bitwise inverted representation of a compressed representation from three binary numbers, wherein:
the 4-to-2-compressor comprises at least one bit cell, wherein the at least one bit cell comprises a first sub-cell belonging to the first sub-circuit and a second sub-cell belonging to the second sub-circuit; and
at least one of the first sub-cell and the second sub-cell comprises three operand inputs, an inverted sum output and an inverted carry output.

2. The circuit of claim 1 , wherein the three operand inputs of the first sub-cell and one operand input of the second sub-cell correspond to four operand inputs of the bit cell of the 4-to-2 compressor.

3. The circuit of claim 1 , wherein one operand input of the second sub-cell corresponds to a carry input of the bit cell.

4. The circuit of claim 1 , wherein an inverted sum output of the second sub-cell corresponds to a sum output of the bit cell and an inverted carry output of the first sub-cell corresponds to an inverted carry output of the bit cell.

5. The circuit of claim 1 , wherein the inverted sum output of the first sub-cell is connected to an operand input of the second sub-cell.

6. The circuit of claim 1 , wherein:
at least one of the first sub-cell and the second sub-cell comprises a XNOR-circuit transmitting the result of a XNOR operation on the three operand inputs as the inverted carry output.

7. The circuit of claim 1 , wherein:
the XNOR-circuit comprises a first PFET, a second PFET, a third PFET, a fourth PFET, a fifth PFET, a first NFET, a second NFET, a third NFET, a fourth NFET, and a fifth NFET;
the drain of the first PFET, the drain of the second PFET and the drain of the third PFET are connected to VDD;
the source of the first NFET, the source of the second NFET, and the source of the third NFET are connected to ground;
the source of the first PFET and the source of the second PFET are connected to the drain of the fourth PFET;
the drain of the first NFET and the drain of the second NFET are connected to the source of the fourth NFET;
the source of the third PFET is connected to the drain of the fifth PFET;
the drain of the third NFET is connected to the source of the fifth NFET;
the drain of the fourth NFET, the drain of the fifth NFET, the source of the fourth PFET;
the source of the fifth PFET are connected to one another and the inverted carry output;
the gate of the first PFET, the gate of the first NFET, the gate of the fifth PFET, the gate of the fifth NFET are connected to a first operand input;
the gate of the second PFET, the gate of the second NFET, the gate of the third PFET and the gate of the third NFET are connected to a second operand input; and
the gate of the fourth PFET and the gate of the fourth NFET are connected to a third operand input.

8. The circuit of claim 7 , wherein:
the NAND-circuit comprises:
a sixth PFET;
a seventh PFET;
an eighth PFET;
a sixth NFET;
a seventh NFET; and
an eighth NFET;

the drain of the sixth PFET, the drain of the seventh PFET and the drain of the eighth PFET are connected to VDD;
the source of the sixth PFET, the source of the seventh PFET and the source of the eighth PFET are connected to one another;
the source of the sixth NFET, the source of the seventh NFET and the source of the eighth NFET are connected to ground;
the drain of the sixth NFET, the drain of the seventh NFET and the drain of the eighth NFET are connected to one another;
the gate of the sixth PFET and the gate of the sixth NFET are connected to the third operand input;
the gate of the seventh PFET and the gate of the seventh NFET are connected to the first operand input;
the gate of the eighth PFET and the gate of the eight NFET are connected to the second operand input;
the AND-circuit comprises:
a ninth PFET; and
a ninth NFET;

the drain of the ninth PFET is connected to the source of the sixth PFET;
the source of the ninth NFET is connected to the drain of the sixth NFET;
the drain of the ninth NFET is connected to the source of the ninth PFET; and
the gate of the ninth NFET and the gate of the ninth PFET are connected; and

wherein the drain of the ninth NFET corresponds to the inverted sum output.

9. The circuit of claim 6 , wherein:
the at least one of the first sub-cell and the second sub-cell comprises an AND-circuit receiving from a NAND-circuit the result of a NAND operation on the three operand inputs and an inverted inverted carry output and transmitting the result as the inverted sum output.

10. The circuit of claim 9 , wherein:
the NAND-circuit comprises a sixth PFET, a seventh PFET, an eighth PFET, a sixth NFET, a seventh NFET, and an eighth NFET;
the drain of the sixth PFET, the drain of the seventh PFET and the drain of the eighth PFET are connected to VDD;
the source of the sixth PFET, the source of the seventh PFET and the source of the eighth PFET are connected to one another;
the source of the sixth NFET, the source of the seventh NFET and the source of the eighth NFET are connected to ground;
the drain of the sixth NFET, the drain of the seventh NFET and the drain of the eighth NFET are connected to one another;
the gate of the sixth PFET and the gate of the sixth NFET are connected to the third operand input;
the gate of the seventh PFET and the gate of the seventh NFET are connected to the first operand input; and
the gate of the eighth PFET and the gate of the eight NFET are connected to the second operand input.

11. The circuit of claim 9 , wherein:
the AND-circuit comprises a ninth PFET, and a ninth NFET;
the drain of the ninth PFET is connected to the source of the sixth PFET;
the source of the ninth NFET is connected to the drain of the sixth NFET;
the drain of the ninth NFET is connected to the source of the ninth PFET;
the gate of the ninth NFET and the gate of the ninth PFET are connected; and
the drain of the ninth NFET corresponds to the inverted sum output.

12. The circuit of claim 9 , wherein;
the NOR-circuit comprises a tenth PFET, an eleventh PFET, a twelfth PFET, a tenth NFET, an eleventh NFET, and a twelfth NFET;
the drain of the tenth PFET is connected to VDD;
the drain of the eleventh PFET is connected to the source of the tenth PFET;
the drain of the twelfth PFET is connected to the source of the eleventh PFET;
the source of the tenth NFET is connected to ground;
the source of the eleventh NFET is connected to the drain of the tenth NFET;
the source of the twelfth NFET is connected to the drain of the eleventh NFET;
the source of the twelfth PFET and the drain of the twelfth NFET are connected to one another and to the output of the NOR-circuit;
the gate of the tenth PFET is connected to one of the first operand input, the second operand input and the third operand input;
the gate of the eleventh PFET is connected to another one of the first operand input, the second operand input and the third operand input;
the gate of the twelfth PFET is connected to the remaining one of the first operand input, the second operand input and the third operand input;
the gate of the tenth NFET is connected to one of the first operand input, the second operand input and the third operand input;
the gate of the eleventh NFET is

Assignees

• IBM

Inventors

• Beck Manuel
• Haller Wilhelm
• Krauch Ulrich
• Lind Kurt
• Schroeder Friedrich

Classifications

• G06F7/50 Primary

  Adding; Subtracting (G06F7/483 - G06F7/491, G06F7/544 - G06F7/556 take precedence) · CPC title

• G06F7/509 Primary

  for multiple operands, e.g. digital integrators · CPC title