Highly efficient inexact computing storage device

Patent metadata

Field	Value
Publication number	US-2016350074-A1
Application number	US-201514838351-A
Country	US
Kind code	A1
Filing date	Aug 27, 2015
Priority date	Jun 1, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

A device ( 105 ) can include storage device ( 110 ) to store data. The device ( 105 ) can also include an accuracy requirement detector ( 120 ). Given an iteration of an algorithm ( 130 ) and the results of previous iterations of the algorithm ( 130 ), accuracy requirement detector ( 120 ) can determine the accuracy required for the current iteration of the algorithm ( 130 ). The device ( 105 ) can also include an adaptive mechanism ( 125 ) that can schedule the iteration of the algorithm ( 130 ) on an available arithmetic logic unit (ALU) based on the accuracy required for the iteration of the algorithm ( 130 ).

First claim

What is claimed is:

1 . A device ( 105 ), comprising:
a storage ( 110 ) to store data ( 135 ); an accuracy requirement detector ( 120 ) to determine a required accuracy ( 205 ) for an iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of an algorithm ( 130 ); and an adaptive mechanism ( 125 ) coupled to the accuracy requirement detector ( 120 ) within the device ( 105 ), the adaptive mechanism ( 125 ) operative to schedule the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ) using the data ( 135 ) across a plurality of available arithmetic logic units (ALUs) ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) based on a required accuracy ( 205 ) for the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ).

2 . A device ( 105 ) according to claim 1 , wherein the available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) include at least one of a processor ( 115 ) in the device ( 105 ), an ALU ( 730 - 1 , 730 - 2 , 730 - 3 ) on a host computer ( 705 ), an ALU ( 755 - 1 , 755 - 2 , 755 - 3 ) on a network computer ( 740 ), a general-purpose computing on graphics processing unit (GPGPU) ( 735 ) on the host computer ( 705 ), and a GPGPU ( 760 ) on the network computer ( 740 ).

3 . A device ( 105 ) according to claim 2 , wherein the available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) further include a configurable ALU ( 140 - 3 ).

4 . A device ( 105 ) according to claim 3 , wherein the configurable ALU ( 140 - 3 ) is operative to receive a number of bits ( 1125 ) to use in executing the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ).

5 . A device ( 105 ) according to claim 3 , wherein the processor ( 115 , 715 , 750 ) includes the configurable ALU ( 140 - 3 ).

6 . A device ( 105 ) according to claim 2 , wherein the available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) include at least a first ALU ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) with a first accuracy ( 305 ) and a second ALU ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) with a second accuracy ( 310 ).

7 . A device ( 105 ) according to claim 2 , wherein the adaptive mechanism ( 125 ) is operative to determine the plurality of available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) by querying ( 805 ) a lookup table ( 815 ).

8 . A device ( 105 ) according to claim 1 , wherein the accuracy requirement detector ( 120 ) is operative to calculate the required accuracy ( 205 ) for the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ) by calculating ( 1415 ) a delta ( 210 ) between results in previous iterations ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ) and comparing the delta ( 210 ) against a threshold ( 215 ).

9 . A device ( 105 ) according to claim 1 , wherein the adaptive mechanism ( 125 ) is operative to receive the required accuracy ( 205 ) for the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ) from the algorithm ( 130 ).

10 . A device ( 105 ) according to claim 1 , wherein:
the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ) includes alternative calculations ( 605 - 1 , 605 - 2 , 605 - 3 , 605 - 4 , 605 - 5 ); and the adaptive mechanism ( 125 ) is operative to select a second plurality of ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) from the plurality of available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ), each of the selected second plurality of ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) operative to execute one alternative calculation ( 605 - 1 , 605 - 2 , 605 - 3 , 605 - 4 , 605 - 5 ) from the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ).

11 . A method, comprising:
receiving ( 1305 , 1310 ) an algorithm ( 130 ) and data ( 135 ) to process using the algorithm ( 130 ); determining ( 1320 ) available arithmetic logic units (ALUs) ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ); determining ( 1325 ) a required accuracy ( 205 ) for an iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ); selecting ( 1330 ) one or more of the available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) based on the required accuracy ( 205 ) for the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ); sending ( 1335 ) the algorithm ( 130 ) and the data ( 135 ) to the selected one or more of the available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ); and requesting ( 1340 ) the selected one or more of the available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) to execute the algorithm ( 130 ) using the data ( 135 ), wherein a system including the available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) is self-configuring to optimize execution of the algorithm ( 130 ) using the data ( 135 ).

12 . A method according to claim 11 , wherein selecting ( 1330 ) one or more of the available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) includes selecting ( 1620 ) a Storage Processing Unit (SPU) on a smart Solid State Drive (SSD) based on the required accuracy ( 205 ) for the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ), wherein the SPU is capable of executing the algorithm ( 130 ) using the data ( 135 ).

13 . A method according to claim 12 , wherein selecting ( 1620 ) an SPU includes selecting ( 1620 ) the SPU on the smart SSD based on the required accuracy ( 205 ) for the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ), the SSD storing the data ( 135 ) to process using the algorithm ( 130 ).

14 . A method according to claim 11 , wherein selecting ( 1330 ) one or more of the available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) based on the required accuracy ( 205 ) for the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ) includes selecting ( 1330 ) one or more of the available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) that is at least as accurate as the required accuracy ( 205 ) for the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ).

15 . A method according to claim 14 , wherein selecting ( 1330 ) one or more of the available ALUs ( 140 - 1 , 140 - 2 , 140 - 3 , 730 - 1 , 730 - 2 , 730 - 3 , 755 - 1 , 755 - 2 , 755 - 3 ) based on the required accuracy ( 205 ) for the iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algorithm ( 130 ) further includes:
determining ( 1410 ) a first result of a first previous iteration ( 505 - 1 , 505 - 2 , 505 - 3 , 505 - 4 ) of the algo

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Inseok Stephen
• Ki Yang Seok

Classifications

• G06F9/50 Primary

  Allocation of resources, e.g. of the central processing unit [CPU] · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F7/57

  Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations {(G06F7/49, G06F7/491 take precedence)} · CPC title

• G06F9/3885

  using a plurality of independent parallel functional units · CPC title

• G06F16/2219

  Large Object storage; Management thereof · CPC title