Semiconductor structure and method for manufacturing a semiconductor structure

Patent metadata

Field	Value
Publication number	US-9864134-B2
Application number	US-201314442240-A
Country	US
Kind code	B2
Filing date	Nov 27, 2013
Priority date	Nov 30, 2012
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a processed semiconductor substrate. The processed semiconductor substrate includes active electronic components. The semiconductor structure also includes a dielectric layer that covers, at least partially, the processed semiconductor substrate. An interface layer that is suitable for growing optically active material on the interface layer is bonded to the dielectric layer. An optical gain layer and the processed semiconductor substrate are connected through the dielectric layer by electric and/or optical contacts.

First claim

The invention claimed is:

1. A semiconductor structure comprising:
a complementary metal-oxide semiconductor (CMOS) wafer comprising:
a silicon substrate,
a processed CMOS layer that overlies the silicon substrate and includes electronic and photonic components,
a passivation layer that overlies the processed CMOS layer and the electronic and photonic components therein, and
a dielectric interlayer that overlies the passivation layer;

a seed layer comprising a III-V material that is bonded to the CMOS wafer at a surface of the dielectric interlayer, and wherein the electronic and photonic components of the processed CMOS layer are communicatively connected to the seed layer by electrical or optical contacts that penetrate the dielectric interlayer; and
a re-growth layer of the III-V material that is epitaxially grown between 450° C. and 650° C. from the seed layer, wherein the electronic and photonic components of the processed CMOS layer are front-end components and are capable of operation after exposure to temperatures between 450° C. and 650° C.

2. The semiconductor structure of claim 1 , wherein the re-growth layer of the III-V material comprises a laser.

3. The semiconductor structure of claim 1 , wherein the re-growth layer of the III-V material comprises an optical amplifier.

4. The semiconductor structure of claim 1 , wherein the re-growth layer of the III-V material comprises a light-emitting diode.

5. The semiconductor structure of claim 1 , wherein the passivation layer comprises silicon nitride.

6. The semiconductor structure of claim 1 , wherein the dielectric interlayer comprises silicon dioxide.

7. The semiconductor structure of claim 1 , wherein the photonic components of the processed CMOS layer comprise one or more silicon-based waveguides.

8. The semiconductor structure of claim 1 , wherein the bonded seed layer is bonded to the surface of the dielectric interlayer between 200° C. and 300° C.

Assignees

• IBM

Inventors

• Czornomaz Lukas
• Fompeyrine Jean
• Hofrichter Jens
• Offrein Bert Jan
• Richter Mirja

Classifications

• H01L27/14

  Electricity · mapped topic

• G02B6/12004 Primary

  Combinations of two or more optical elements · CPC title

• H01L31/18

  Electricity · mapped topic

• Y02P70/521

  Cross-Sectional Technologies · mapped topic

• H10F99/00 Primary

  Subject matter not provided for in other groups of this subclass · CPC title