Critical dimension shrink through selective metal growth on metal hardmask sidewalls

US10168075B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10168075-B2
Application numberUS-201815907812-A
CountryUS
Kind codeB2
Filing dateFeb 28, 2018
Priority dateJun 1, 2015
Publication dateJan 1, 2019
Grant dateJan 1, 2019

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.

First claim

Opening claim text (preview).

What is claimed is: 1. A self-aligned via structure, comprising: an inter-level dielectric (ILD) layer arranged on a metal wiring layer; a trench arranged within the ILD layer; a via arranged substantially perpendicular to the trench and extending through an area of the trench, the via further extending into a portion of the metal wiring layer; and a metal capping layer lining sidewalls of the via at the area where the via extends through the trench. 2. The self-aligned via structure of claim 1 , wherein the metal capping layer has a thickness of about 1 nm to about 10 nm. 3. The self-aligned via structure of claim 1 , further comprising a metal filling the trench and the via. 4. The self-aligned via structure of claim 1 , wherein the trench has a width in a range from about 5 nm to about 50 nm. 5. The self-aligned via structure of claim 4 , wherein the via has a width that is less than the trench. 6. The self-aligned via structure of claim 1 , wherein the metal wiring layer is copper. 7. The self-aligned via structure of claim 1 , wherein the metal wiring layer is a copper alloy. 8. The self-aligned via structure of claim 1 , wherein the metal wiring layer is manganese, manganese alloys, cobalt, cobalt alloys, tungsten, tungsten alloys, or any combination thereof. 9. The self-aligned via structure of claim 1 , wherein the via and the trench further comprise a barrier metal layer liner and a copper filling. 10. The self-aligned via structure of claim 9 , wherein the barrier metal layer liner is tantalum, tantalum nitride, titanium nitride, titanium tungstate, or a combination thereof. 11. A dual damascene structure, comprising: a trench arranged within an inter-level dielectric (ILD) layer; and a via arranged substantially perpendicular to the trench, self-aligned with the trench, and extending through an area of the trench, the via further extending through the ILD layer and into a portion of a metal wiring layer beneath the ILD layer; wherein the via has a width that is less than the trench at the area that extends through with the trench. 12. The dual damascene structure of claim 11 , further comprising a barrier metal lining the via and the trench within the ILD layer and the metal wiring layer. 13. The dual damascene structure of claim 12 , further comprising copper filling the trench and the via. 14. The dual damascene structure of claim 11 , wherein the trench has a width in a range from about 5 nm to about 50 nm. 15. The dual damascene structure of claim 11 , wherein the metal wiring layer is copper. 16. The dual damascene structure of claim 11 , wherein the metal wiring layer is a copper alloy. 17. The dual damascene structure of claim 11 , wherein the metal wiring layer is manganese, manganese alloys, cobalt, cobalt alloys, tungsten, tungsten alloys, or any combination thereof. 18. The dual damascene structure of claim 11 , wherein the via and the trench further comprise a barrier metal layer liner and a copper filling. 19. The dual damascene structure of claim 18 , wherein the barrier metal layer is tantalum nitride. 20. The dual damascene structure of claim 19 , wherein the barrier metal layer liner is tantalum, titanium nitride, titanium tungstate, or a combination thereof.

Assignees

Inventors

Classifications

  • H10P50/73Primary

    using masks for insulating materials · CPC title

  • Barrier, adhesion or liner layers · CPC title

  • using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

  • involving partial etching of via holes · CPC title

  • involving multiple stacked pre-patterned masks · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10168075B2 cover?
A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via patte…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10P50/73. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).