Circuit and layout for single gate type precharge circuit for data lines in memory device

Patent metadata

Field	Value
Publication number	US-10163906-B2
Application number	US-201615293554-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Oct 14, 2016
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.

First claim

What is claimed is:

1. An apparatus comprising:
a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region;
a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region, wherein the first channel region, the portion of the first diffusion region, and the portion of the third diffusion region form part of a first transistor;
a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region, wherein the second channel region, the portion of the third diffusion region, and the portion of the second diffusion region form part of a second transistor;
a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region, wherein the third channel region, the portion of the second diffusion region, and the portion of the fourth diffusion region form part of a third transistor; and
a gate located over the first, second, and third channel regions, wherein the gate is shared by the first, second, and third transistors, and wherein the first and second diffusion regions are located on a first side of the gate, and the third and fourth diffusion regions, are located on a second side of the gate opposite from the first side.

2. The apparatus of claim 1 , further comprising:
a fourth channel region located between another portion of the first diffusion region and another portion of the second diffusion region;
a fifth channel region located between another portion of the third diffusion region and another portion of the fourth diffusion region;
a second gate located over the fourth channel region; and
a third gate located over the fifth channel region.

3. The apparatus of claim 2 , wherein the first and fourth diffusion regions are electrically coupled to each other, the second diffusion region and the third gate are electrically coupled to each other, and the third diffusion region and the second gate are electrically coupled to each other.

4. The apparatus of claim 2 , wherein the gate located over the first, second, and third channel regions includes a length extending in a first direction, and each of the second and third gates includes a length extending in a second direction, and the first direction is perpendicular to the second direction.

5. The apparatus of claim 1 , wherein the gate extends generally linearly between the first and second diffusion regions on the first side and between the third and fourth diffusion regions on the second side.

6. The apparatus of claim 1 , wherein the gate includes a first portion located over the first channel region, a second portion located over the second channel region, and a third portion located over the third channel region, the second portion of the gate is between the first and third portions of the gate, and the second portion of the gate is narrower than each of the first and third portions of the gate.

7. The apparatus of claim 1 , wherein the second diffusion region includes an elongated portion, and the portion of the second diffusion region is part of the elongated portion.

8. The apparatus of claim 7 , wherein the third diffusion region includes an elongated portion, and the portion of the third diffusion region is part of the elongated portion of the third diffusion region.

9. The apparatus of claim 1 , wherein the first diffusion region includes an elongated portion, and the portion of the first diffusion region is part of the elongated portion.

10. The apparatus of claim 9 , wherein the fourth diffusion region includes an elongated portion, and the portion of the fourth diffusion region is part of the elongated portion of the fourth diffusion region.

11. The apparatus of claim 1 , wherein each of the first, second, third, and fourth diffusion regions includes a material of a first conductivity type, and each of the first, second, and third channel regions includes a material of a second conductivity type.

12. The apparatus of claim 1 , wherein the apparatus comprises a memory device, the memory device comprising:
a first memory cell array located at a first location of the memory device; and
a second memory cell array located at a second location of the memory device, wherein the first, second, third, and fourth diffusions are located at a third location of the memory device between the first and second locations.

13. The apparatus of claim 1 , wherein the apparatus comprises a memory device, and the first, second, third, and fourth diffusion regions are part of sensing circuitry of the memory device.

14. An apparatus comprising:
a first diffusion region including a first elongated portion, a second diffusion region including a second elongated portion, a third diffusion region including a third elongated portion, and a fourth diffusion region including a fourth elongated portion;
a first channel region located between the first and third elongated portions, wherein the first channel region and the first and third elongated portions form part of a first transistor;
a second channel region located between second and third elongated portions, wherein the second channel region and the second and third elongated portions form part of a second transistor;
a third channel region located between the second and fourth elongated portions, wherein the third channel region and the second and fourth elongated portions form part of a third transistor;
a gate located over the first, second, and third channel regions, wherein the gate is shared by the first, second, and third transistors, and wherein the first and second diffusion regions are located on a first side of the gate, and the third and fourth diffusion regions are located on a second side of the first gate opposite from the first side; and
a conductive line electrically coupled to the first and fourth diffusion regions.

15. The apparatus of claim 14 , further comprising:
a first conductive contact coupled to the second diffusion region;
a first data line coupled to the second conductive contact;
a second conductive contact coupled to the third diffusion region; and
a second data line coupled to the third conductive contact.

16. The apparatus of claim 14 , further comprising:
a first conductive contact coupled to the first diffusion region; and
a second conductive contact coupled to the fourth diffusion region, wherein the conductive line is electrically coupled to the first and fourth diffusion regions through the first and second conductive contacts, respectively.

17. The apparatus of claim 14 , wherein the apparatus comprises a memory device, the memory device comprising a memory cell array and access lines located at a first location of the memory device, wherein the conductive line is located at a second location of the memory device, and each of the access lines and the conductive line has a length extending in a same direction.

Assignees

• Micron Technology Inc

Inventors

• Miyatake Shinichi

Classifications

• H01L27/108 Primary

  Electricity · mapped topic

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C7/08

  Control thereof · CPC title

• H01L27/11286

  Electricity · mapped topic

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title