Recessed and embedded die coreless package

Patent metadata

Field	Value
Publication number	US-10163863-B2
Application number	US-201615375112-A
Country	US
Kind code	B2
Filing date	Dec 11, 2016
Priority date	Dec 29, 2009
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

First claim

What is claimed is:

1. A package structure, comprising:
a dielectric layer having a top surface and a fillet structure that extends from the dielectric layer top surface;
a die having a top surface, first and second sidewalls, and an active surface opposite the top surface, wherein the die is at least partially embedded in the fillet structure of the dielectric layer;
wherein the fillet structure of the dielectric layer has a sloped portion extending from the top surface of the dielectric layer to a position adjacent the top surface of the die, wherein the top surface of the die is free from the dielectric layer and is substantially coplanar with the top surface of the dielectric layer, and wherein the fillet structure of the dielectric layer surrounds the first and second sidewalls and the active surface of the die;
a package-on-package land area adjacent the fillet structure at the top surface of the dielectric layer;
a package-on-package land interconnect structure extending into the dielectric layer and electrically connected to the package-on-package land area, to receive another package structure in response to attachment of the other package structure to the package structure; and
an interconnect structure extending into the dielectric layer and electrically connected to the active surface of the die.

2. The package structure of claim 1 , further comprising at least one additional dielectric layer formed on the dielectric layer and a metallization layer extending through the at least one additional dielectric layer to electrically contact at least one of the package-on-package land interconnect structure and the interconnect structure.

3. The package structure of claim 1 , further comprising an adhesive film on the top surface of the die.

Assignees

• Intel Corp

Inventors

• Guzek John

Classifications

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/9413

  on encapsulations · CPC title