Sinker with a reduced width

Patent metadata

Field	Value
Publication number	US-10163678-B2
Application number	US-201514682823-A
Country	US
Kind code	B2
Filing date	Apr 9, 2015
Priority date	Jul 2, 2012
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Forming a semiconductor structure by forming a plurality of trenches in a semiconductor material, forming a plurality of non-conductive structures in the plurality of trenches, and forming a doped region of the first conductivity type. The plurality of trenches are spaced apart from each other, have substantially equal depths, and include a first trench and a second trench. The plurality of non-conductive structures include a first non-conductive structure in the first trench and a second non-conductive structure in the second trench. The doped region is formed between the first non-conductive structure and the second non-conductive structure. No region of a second conductivity type lies horizontally in between the first non-conductive structure and the second non-conductive structure.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
forming a plurality of trenches in a semiconductor material, the plurality of trenches being spaced apart from each other, having substantially equal depths, and including a first trench and a second trench;
forming a plurality of non-conductive structures in the plurality of trenches, the plurality of non-conductive structures being spaced apart and including a first non-conductive structure in the first trench and a second non-conductive structure in the second trench; and
after forming the plurality of trenches, forming a doped region in between and touching the first non-conductive structure and the second non-conductive structure using first and second implant steps and first and second anneals, the doped region having a first conductivity type, no region of a second conductivity type lying horizontally in between the first non-conductive structure and the second non-conductive structure; and
forming a horizontal portion of the doped region that touches the top surface of the semiconductor material, extends to a depth less than a depth of the first and second isolation structures, and extends continuously from the first non-conductive structure to the second non-conductive structure, the horizontal portion having a substantially uniform dopant concentration.

2. The method of claim 1 wherein:
the first non-conductive structure includes a first interior side wall surface, a first exterior side wall surface, and a first bottom surface that connects the first interior side wall surface to the first exterior side wall surface; and
the second non-conductive structure includes a second interior side wall surface, a second exterior side wall surface, and a second bottom surface that connects the second interior side wall surface to the second exterior side wall surface.

3. The method of claim 2 wherein the doped region touches the first exterior side wall surface and extends continuously from the first exterior side wall surface to touch the second exterior side wall surface.

4. The method of claim 3 wherein:
a portion of the doped region extends around the first bottom surface and partially up the first interior side wall surface to lie vertically spaced apart from a top surface of the semiconductor material; and
a portion of the doped region extends around the second bottom surface and partially up the second interior side wall surface to lie vertically spaced apart from a top surface of the semiconductor material.

5. The method of claim 4 and further comprising forming a well of the first conductivity type that touches the first interior side wall surface and a top surface of the semiconductor material.

6. The method of claim 4 wherein the first non-conductive structure includes a polysilicon core and a non-conductive outer structure that touches a side wall surface and a bottom surface of the polysilicon core.

7. The method of claim 4 and further comprising:
forming a non-conductive layer that touches a top surface of the semiconductor material; and
forming a metallic contact that extends through the non-conductive layer to make an electrical connection with the doped region.

8. A method of forming a semiconductor structure comprising:
forming a plurality of trenches in a semiconductor material, the plurality of trenches being spaced apart from each other and including a first trench and a second trench;
forming a plurality of isolation structures in the plurality of trenches, the plurality of isolation structures being spaced apart and including a first isolation structure in the first trench and a second isolation structure in the second trench; and
forming a sinker by:
performing a first implant to implant a dopant into the semiconductor material between the first and second isolation structures;
annealing the dopant of the first implant to form a doped region in the semiconductor material;
performing a second implant to implant further dopant into the doped region; and
annealing the doped region after performing the second implant to extend the doped region under the first and second trenches and up an opposite side of the first trench and the second trench, the doped region having a first conductivity type, no region of a second conductivity type lying horizontally in between the first isolation structure and the second isolation structure.

9. The method of claim 8 wherein:
the first isolation structure includes a first interior side wall surface, a first exterior side wall surface, and a first bottom surface that connects the first interior side wall surface to the first exterior side wall surface; and
the second isolation structure includes a second interior side wall surface, a second exterior side wall surface, and a second bottom surface that connects the second interior side wall surface to the second exterior side wall surface.

10. The method of claim 9 , wherein the doped region touches the first exterior side wall surface and extends continuously from the first exterior side wall surface to touch the second exterior side wall surface.

11. The method of claim 10 , wherein:
a portion of the doped region extends around the first bottom surface and partially up the first interior side wall surface to lie vertically spaced apart from a top surface of the semiconductor material; and
a portion of the doped region extends around the second bottom surface and partially up the second interior side wall surface to lie vertically spaced apart from a top surface of the semiconductor material.

12. The method of claim 11 , and further comprising forming a well of the first conductivity type that touches the first interior side wall surface and a top surface of the semiconductor material.

13. The method of claim 11 , wherein the first isolation structure includes a polysilicon core and a non-conductive outer structure that touches a side wall surface and a bottom surface of the polysilicon core.

14. The method of claim 11 , and further comprising:
forming a non-conductive layer that touches a top surface of the semiconductor material; and
forming a metallic contact that extends through the non-conductive layer to make an electrical connection with the doped region.

15. The method of claim 8 , wherein forming the sinker includes forming a horizontal portion of the doped region that touches the top surface of the semiconductor material, extends to a depth less than a depth of the first and second isolation structures, and extends continuously from the first isolation structure to the second isolation structure, the horizontal portion having a substantially uniform dopant concentration.

Assignees

• Texas Instruments Inc

Inventors

• Hu Binghua
• Pendharkar Sameer
• Mathur Guru
• Tamura Takehito

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10P14/66

  characterised by the type of materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W10/0145 Primary

  of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence) · CPC title