Test architecture having multiple FPGA based hardware accelerator blocks for testing multiple DUTs independently

Patent metadata

Field	Value
Publication number	US-10162007-B2
Application number	US-201313773569-A
Country	US
Kind code	B2
Filing date	Feb 21, 2013
Priority date	Feb 21, 2013
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.

First claim

What is claimed is:

1. An automated test equipment (ATE) apparatus comprising:
a computer system comprising a system controller, wherein said system controller, using a network switch, is communicatively coupled to a site module board comprising a tester processor and a plurality of FPGAs, wherein said system controller is operable to transmit instructions to said tester processor, and wherein said tester processor is operable to generate commands and data from said instructions for coordinating testing of a plurality of devices under test (DUTs);
the plurality of FPGA components are communicatively coupled to said tester processor via a bus on said site module board, wherein each of said plurality of FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from said tester processor for testing a DUT of a plurality of DUTs; and
a plurality of I/O ports, each for communicating with a respective DUT and each communicatively coupled to a respective FPGA of said plurality of FPGAs, and
wherein said tester processor is configured to operate in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between said tester processor and said plurality of FPGA components in a different manner, wherein said plurality of functional modes comprises a hardware accelerator pattern generator mode, wherein, in the hardware accelerator pattern generator mode: said tester processor is configured to generate all commands for coordinating testing of a plurality of DUTs; and said hardware accelerator circuits of said plurality of FPGA components perform a step selected from the group comprising: generate test pattern data, write said test pattern data to said plurality of DUTs and compare the data read from said plurality of DUTs.

2. The apparatus of claim 1 further comprising a plurality of memory devices wherein each memory device is coupled to one of said plurality of FPGA components and wherein each memory device stores test pattern data to be written to one of said plurality of DUTs.

3. The apparatus of claim 2 wherein said functional modes comprise four functional modes comprising a bypass mode, said hardware accelerator pattern generator mode, a hardware accelerator memory mode and a hardware accelerator packet builder mode.

4. The apparatus of claim 3 wherein, in the bypass mode, the tester processor is configured to generate all commands and data for coordinating testing of said plurality of DUTs.

5. The apparatus of claim 4 wherein, in said bypass mode, said bus carries the command and data load for said plurality of DUTs connected to said tester processor.

6. The apparatus of claim 3 wherein, in the hardware accelerator memory mode: said tester processor is configured to generate all commands for coordinating testing of said plurality of DUTs; and said hardware accelerator circuits of said plurality of FPGA components perform a step selected from the group comprising: read said test pattern data from said memory device, write said test pattern data to said plurality of DUTs and compare the data read from said plurality of DUTs.

7. The apparatus of claim 6 wherein, in said hardware accelerator memory mode, said bus carries only the command load for said plurality of DUTs connected to said tester processor.

8. The apparatus of claim 3 wherein, in the hardware accelerator packet builder mode, the hardware accelerator circuits of said plurality of FPGA components are configured to generate both test data and command data for coordinating testing of said plurality of DUTs.

9. The apparatus of claim 8 wherein, in the hardware accelerator packet builder mode, said bus carries only parameter information from said tester processor to said hardware accelerator circuits of said plurality of FPGA components.

10. The apparatus of claim 1 wherein, in said hardware accelerator pattern generator mode, said bus carries only the command load for said plurality of DUTs connected to said tester processor.

11. The apparatus of claim 1 wherein said plurality of functional modes comprises a hardware accelerator memory mode, wherein in the hardware accelerator memory mode: said tester processor is configured to generate all commands for coordinating testing of said plurality of DUTs; and said hardware accelerator circuits of said plurality of FPGA components perform a step selected from the group comprising: read said test pattern data from said memory device, write said test pattern data to said plurality of DUTs and compare the data read from said plurality of DUTs.

12. The apparatus of claim 1 wherein said plurality of functional modes comprises a hardware accelerator packet builder mode, wherein in the hardware accelerator packet builder mode, the hardware accelerator circuits of said plurality of FPGA components are configured to generate both test data and command data for coordinating testing of said plurality of DUTs.

13. The apparatus of claim 1 wherein said plurality of functional modes comprises a bypass mode, wherein the bypass mode comprises generating all commands and data for coordinating testing of said plurality of DUTs using said tester processor.

14. A method for testing using an automated test equipment (ATE) comprising:
transmitting instructions from a system controller of a computer system to a tester processor, wherein said system controller, using a network switch, is communicatively coupled to a site module board comprising the tester processor and a plurality of FPGAs, wherein said tester processor is operable to generate commands and data from said instructions for coordinating testing of a plurality of devices under test (DUTs);
generating commands and data transparently from said tester processor for testing of a plurality of DUTs using hardware accelerator circuits programmed within a plurality of FPGA components, wherein said plurality of FPGA components is communicatively coupled to said tester processor via a bus on said site module board and wherein each hardware accelerator circuit is operable to test a DUT of said plurality of DUTs;
communicating with a respective DUT through an I/O port, wherein said I/O port is communicatively coupled to a respective FPGA of said plurality of FPGAs; and
operating the tester processor in one of a plurality of functional modes, wherein each functional mode is configured to allocate functionality for generating commands and for generating data between said tester processor and said plurality of FPGA components in a different manner, wherein said plurality of functional modes comprises a hardware accelerator pattern generator mode, wherein the hardware accelerator pattern generator mode further comprises: generating all commands for coordinating testing of a plurality of DUTs using said tester processor; and using said hardware accelerator circuits to perform a step selected from the group comprising: generating all test pattern data, writing said test pattern data and comparing the test pattern data read from said plurality of DUTs.

15. The method of claim 14 further comprising storing test pattern data to be written to said plurality of DUTs to a plurality of memory devices, wherein each memory device is coupled to one of said plurality of FPGA components.

16. The method of claim 15 wherein said functional modes comprise four functional modes comprising a bypass mode, the hardware accelerator pattern generator mode, a hardware accelerator memory mode and a hardware accelerator packet buil

Assignees

• Advantest Corp

Inventors

• Chan Gerald
• Kushnick Eric
• Su Mei-Mei
• Niemic Andrew Steele

Classifications

• G01R31/31724

  Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title

• G01R31/31919

  Storing and outputting test patterns (G01R31/31924 takes precedence; arithmetic and random test patterns generator) · CPC title

• G01R31/31907 Primary

  Modular tester, e.g. controlling and coordinating instruments in a bus based architecture · CPC title

• G06F11/263

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G11C29/56

  External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor · CPC title