Test architecture having multiple FPGA based hardware accelerator blocks for testing multiple DUTs independently
US-10162007-B2 · Dec 25, 2018 · US
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Chan Gerald patents
Chan Gerald is listed as an inventor on 1 patent in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chan Gerald |
| Total patents | 1 |
| First publication | Dec 25, 2018 |
| Latest publication | Dec 25, 2018 |
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Advantest Corp | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G01R31/31724 | 1 |
| G01R31/31919 | 1 |
| G01R31/31907 | 1 |
| G06F11/263 | 1 |
| G11C29/56 | 1 |