Automatic gain control for received signal strength indication

Patent metadata

Field	Value
Publication number	US-10158336-B2
Application number	US-201715627214-A
Country	US
Kind code	B2
Filing date	Jun 19, 2017
Priority date	Mar 4, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

In some implementations, an automatic gain control (AGC) circuit comprises: a pre-divider circuit operable to pre-divide an input signal according to a pre-divider circuit setting and output a pre-divided signal; a pre-amplifier operable to pre-amplify the pre-divided signal and output a pre-amplified signal; a post-divider circuit operable to post-divide the pre-amplified signal according to a post-divider circuit setting; an analog-to-digital converter (ADC) operable to generate a digital data stream from the post-divided signal; logic operable to sample the digital data stream; determine a pre-divider circuit setting and a post-divider circuit setting based on the sampled data stream; set the pre-divider circuit and the post-divider circuit based on the determined settings; and generate a received signal strength value based on the pre-divider circuit setting and the post-divider circuit setting.

First claim

The invention claimed is:

1. A vehicle access system comprising:
a transducer operable to generate a continuous waveform (CW) voltage signal in response to an electro-magnetic or pure magnetic field;
an automatic gain control (AGC) circuit coupled to the transducer, the AGC circuit including two or more divider circuits coupled in series that are operable to divide the voltage signal to improve measurement accuracy;
an analog-to-digital converter (ADC) operable to convert the divided voltage signal into a digital data stream; and
logic operable to:
determine at least one setting for at least one of the divider circuits based on the digital data stream; and
generate a received signal strength value based on the at least one setting.

2. The AGC circuit of claim 1 , wherein the digital data stream represents an instantaneous amplitude of the voltage signal at the ADC input during a current period of the voltage signal.

3. The AGC circuit of claim 1 , wherein at least one of the divider circuits is configured to have different resolutions.

4. The AGC circuit of claim 1 , further comprising:
an amplifier circuit between at least one of the divider circuits and the ADC input, the amplifier circuit operable to amplify the divided voltage signal.

5. The AGC circuit of claim 1 , further comprising:
a bandpass filter inserted between the transducer and the input of the ADC.

6. The AGC circuit of claim 1 , wherein at least one of the divider circuits is operable to bypass the voltage signal based on a strength of the voltage signal and at least one of the divider circuits is operable to bypass the voltage signal based on a strength of the voltage signal.

7. The AGC circuit of claim 1 , wherein at least one of the divider circuits is configured as a logarithmic divider.

8. The AGC circuit of claim 1 , wherein the ADC is a flash ADC.

9. The AGC circuit of claim 8 , wherein the flash ADC is an offset compensated flash ADC.

10. The AGC circuit of claim 1 , wherein the logic is further operable to:
sample the digital data stream over a period of the voltage signal;
detect a peak value from the sample; and
determine at least one setting for at least one of the divider circuits based on the detected peak value.

11. The AGC circuit of claim 1 , wherein the logic is further operable to:
sample the digital data stream ninety degrees after a zero crossing of the voltage signal; and
determine at least one setting for at least one of the divider circuits based on the detected peak value.

12. The AGC circuit of claim 1 , wherein at least one of the divider circuits is configured to have input impedance that is substantially constant for all divider circuit settings.

13. The AGC circuit of claim 1 , wherein the logic is further configured to send feedback values to at least one of the divider circuits every n period(s) of the voltage signal for use in setting at least one of the divider circuits, where n is a positive integer greater or equal to one.

14. The AGC circuit of claim 13 , wherein the feedback values are averaged to reduce an amount of data.

15. The AGC circuit of claim 14 , wherein the feedback values are averaged based on at least one of a number of feedback values that occurred during a time period.

16. The AGC circuit of claim 1 , wherein the received signal strength values are determined by ADC samples in combination with values of at least one of the divider circuits.

17. The AGC circuit of claim 1 , wherein the AGC circuit is further configured to:
store calibration data for individual attenuations of at least one of the divider circuits to increase an accuracy over a complete range of received signal strength values.

18. The AGC circuit of claim 1 , where the logic is further configured to:
enforce at least one of the dividers to a range setting;
measure one or more averaged values of at least one of the dividers that result from the voltage signal at the AGC circuit input after the AGC circuit has settled in a first calibration measurement;
enforce at least one of the dividers to a next range setting and measure one or more averaged values of at least one of the dividers that result from the voltage signal at the AGC circuit input after the AGC circuit has settled and by maintaining an amplitude of the voltage signal at a level related to a preceding measurement for a second calibration measurement;
store a difference of the values derived from the first and second calibration measurements as a calibration value;
repeat the calibration measurement and store steps for other ranges; and
calculate each received signal strength value from a current measured value and from a summation of stored calibration values of ranges which are less than or equal to a current range setting.

19. The AGC circuit of claim 1 , wherein the divider circuits are part of a chain of circuits that are coupled in series and include a pre-divider circuit, followed by pre-amplifier circuit, followed by a post-divider circuit.

20. The AGC circuit of claim 19 , wherein the divider circuits are part of a chain of circuits that are coupled in series and include a pre-divider circuit, followed by pre-amplifier circuit, followed by a post-divider circuit, followed by a post-amplifier circuit.

Assignees

• Atmel Corp

Inventors

• Blatz Werner
• Sagebiel Michael
• Janz Thomas
• Fischer Martin
• Moser Daniel
• Knopf Jan

Classifications

• H04B17/21

  for calibration; for correcting measurements · CPC title

• H04B17/318 Primary

  Received signal strength · CPC title

• H03G3/3084

  in receivers or transmitters for electromagnetic waves other than radiowaves, e.g. lightwaves (H03G3/32, H03G3/34 take precedence) · CPC title

• H03G3/3036 Primary

  in high-frequency amplifiers or in frequency-changers (H03G3/3052, H03G3/32, H03G3/34 take precedence) · CPC title

• H03G3/3052

  in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver (H03G3/32, H03G3/34 take precedence) · CPC title