High dynamic range radio architecture with enhanced image rejection

Patent metadata

Field	Value
Publication number	US-9246719-B2
Application number	US-201414319992-A
Country	US
Kind code	B2
Filing date	Jun 30, 2014
Priority date	Jan 5, 2010
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

A circuit for down-converting an RF signal to a baseband signal includes a trans-admittance amplifier adapted to receive the RF signal and generate in response a pair of differential current signals. The circuit further includes a trans-impedance amplifier having at least four mixers and at least four linear amplifiers. The four mixers frequency down-convert the pair of differential current signals to generate four pairs of differential baseband current signals, wherein each pair of the differential baseband current signals has a different phase and is associated with each of the linear amplifiers. Additionally, the circuit includes a summing block that generates an in-phase signal using a first weighted sum of the four different baseband current signals and a quadrature signal using a second weighted sum of the four different baseband current signals. The circuit further includes an analog-to-digital converter for converting the in-phase and quadrature signals to respective digital representations.

First claim

What is claimed is:

1. A circuit comprising:
a trans-admittance amplifier (TAA) receiving a Radio Frequency (RF) signal and in response generating a pair of differential RF current signals at a positive TAA output terminal and a negative TAA output terminal, the trans-admittance amplifier comprising:
a low-noise amplifier (LNA) for receiving the RF signal at an input LNA terminal, amplifying the received RF signal, and outputting the amplified RF signal on an output LNA terminal;
a first gain stage for receiving the amplified RF signal at a first stage input capacitively coupled to the output LNA terminal, applying a first gain to the amplified RF signal to generate the positive RF current signal of the pair of differential RF current signals, and outputting the positive RF current signal on a first stage output capacitively coupled to the positive TAA output terminal; and
a second gain stage for receiving the RF signal on a second stage input capacitively coupled to the input LNA terminal, applying a second gain to the received RF signal to generate the negative RF current signal of the pair of differential RF current signals, and outputting the negative RF current signal on a second stage output capacitively coupled to the negative TTA output terminal;
a second amplifier circuit comprising at least four mixers and at least four linear amplifiers, the at least four mixers down-converting a frequency of the pair of differential RF current signals from the positive and negative TAA output terminals to generate four pairs of differential baseband current signals each having a phase corresponding to different phases of a local oscillator signal, and each of the linear amplifiers being associated with a different one of the four pairs of differential baseband current signals; and
a summing block configured to:
generate an in-phase signal using a first weighted sum of the four differential baseband current signals; and
generate a quadrature phase signal using a second weighted sum of the four differential baseband current signals; and

a processing unit configured to reduce harmonics in at least one of the lour pairs of differential baseband current signals based on the generated in-phase and quadrature harmonic signals.

2. The circuit of claim 1 , wherein a first one of the four pairs of the differential baseband current signal has a phase of 0 degree with respect to the local oscillator signal, wherein a second one of the four pairs of the differential baseband current signal has a phase of 45 degrees with respect to the local oscillator signal, wherein a third one of the four pairs of the differential baseband current signal has a phase of 90 degrees with respect to the local oscillator signal, wherein a fourth one of the four pairs of the differential baseband current signal has a phase of 135 degrees with respect to the local oscillator signal.

3. The circuit of claim 2 , wherein each of the at least four mixers receives two 12.5% duty cycle non-overlapping clock signals to provide one of the four pairs of differential baseband current signals.

4. The circuit of claim 1 , wherein a first pair of the four pairs of differential baseband current signals is defined as TZ 0 having a relative phase of 0 degrees, a second pair of the four pairs of differential baseband current signals is defined as TZ 45 having a relative phase of 45 degrees, a third pair of the four pairs of differential baseband current signals is defined as TZ 90 having a relative phase of 90 degrees, a fourth pair of the four pairs of differential baseband current signals is defined as TZ 135 having a relative phase of 135 degrees, and the generated in-phase signal using the first weighted sum of the four differential baseband current signals is substantially equal to:
TZ 0 +(√2+1) TZ 45 +(√2+1) TZ 90 +TZ 135 .

5. The circuit of claim 1 , wherein a first pair of the four pairs of differential baseband current signals is defined as TZ 0 having a relative phase of 0 degrees, a second pair of the four pairs of differential baseband current signals is defined as TZ 45 having a relative phase of 45 degrees, a third pair of the four pairs of differential baseband current signals is defined as TZ 90 having a relative phase of 90 degrees, a fourth pair of the four pairs of differential baseband current signals is defined as TZ 135 having a relative phase of 135 degrees, and the generated quadrature signal using the second sum of the four differential baseband current signals is substantially equal to:
(√2+1) TZ 0 +TZ 45 +TZ 90 +(√2+1) TZ 135 .

6. A circuit for reducing harmonics in a received signal comprising:
a trans-admittance amplifier (TAA) receiving a Radio Frequency (RF) signal and in response generating a pair of differential RF current signals at a positive TAA output terminal and a negative TAA output terminal, the trans-admittance amplifier comprises:
a low-noise amplifier (LNA) for receiving the RF signal at an input LNA terminal, amplifying the received RF signal, and outputting the amplified RF signal on an output LNA terminal;
a first gain stage for receiving the amplified RF signal at a first stage input capacitively coupled to the output LNA terminal, applying a first gain to the amplified RF signal to generate the positive RF current signal of the pair of differential RF current signals, and outputting the positive RF current signal on a first stage output capacitively coupled to the positive TAA output terminal; and
a second gain stage for receiving the RF signal on a second stage input capacitively coupled to the input LNA terminal, applying a second gain to the received RF signal to generate the negative RF current signal of the pair of differential RF current signals, and outputting the negative RF current signal on a second stage output capacitively coupled to the negative TTA output terminal;

a second amplifier circuit comprising at least four mixers and at least four linear amplifiers, the at least four mixers down-converting a frequency of the pair of differential RF current signals from the positive and negative TAA output terminals to generate four pairs of differential baseband current signals each having a phase corresponding to different phases of a local oscillator signal, and each of the linear amplifiers being associated with a different one of the four pairs of differential baseband current signals; and
a summing block configured to:
generate an in-phase harmonic signal using a first weighted sum of at least a first set of three of the four pairs of differential baseband current signals; and
generate a quadrature harmonic signal using a second weighted sum of at least a second set of three of the four pairs of differential baseband current signals; and

a processing unit configured to reduce harmonics in at least one of the four pairs of differential baseband current signals based on the generated in-phase and quadrature harmonic signals.

7. The circuit of claim 6 , further comprising:
an analog-to-digital converter module configured to convert the at least one of the four pairs of differential baseband current signals and the in-phase and quadrature harmonic signals to respective digital representations.

8. The circuit of claim 6 , wherein the processing unit is a digital signal processor configured to eliminate the harmonics out of the at least one of the four pairs of differential baseband current signals using a least means squares algorithm based on the generated in-phase and quadrature harmonic signals.

9. The circuit of claim 6 , further comprising:
a local oscillator including a multi-phase signal generator configured to produce a plurality of clock signals having a same frequency and d

Assignees

• Maxlinear Inc
• Maxliner Inc

Inventors

• Pullela Raja
• Su Yu
• Chen Wenjian

Classifications

• H03D7/165 Primary

  at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature (combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002) · CPC title

• H04B1/30

  for homodyne or synchrodyne receivers (demodulator circuits H03D1/22) · CPC title

• H04L25/08 Primary

  Modifications for reducing interference; Modifications for reducing effects due to line faults {; Receiver end arrangements for detecting or overcoming line faults} · CPC title