Amplifiers operating in envelope tracking mode or non-envelope tracking mode

Patent metadata

Field	Value
Publication number	US-10158328-B2
Application number	US-201715618452-A
Country	US
Kind code	B2
Filing date	Jun 9, 2017
Priority date	Dec 28, 2012
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

Various envelope tracking amplifiers are presented that can be switched between an ET (envelope tracking) mode and a non-ET mode. Switches and/or tunable components are utilized in constructing the envelope tracking amplifiers that can be switched between the ET mode and the non-ET mode.

First claim

The invention claimed is:

1. An amplifier arrangement configured to operate based on a mode of operation, comprising:
an adjustable power supply controlled by a first control signal to provide either a variable supply or a constant supply to the amplifier arrangement; and
a power amplifier comprising a configuration arrangement controlled by secondary control signals, the configuration arrangement adapted to configure the power amplifier based on the mode of operation,
wherein
the mode of operation comprises a first mode of operation and a second mode of operation selectable via a first supply switch, the first mode of operation corresponding to the adjustable power supply providing variable supply to the power amplifier, the second mode of operation corresponding to the adjustable power supply providing constant supply to the power amplifier, the mode of operation switching between the first mode of operation and the second mode of operation and vice versa based on an input signal to the power amplifier, and
the adjustable power supply is configured to provide:
a bias voltage to a drain of a transistor of the power amplifier and a bias voltage to a gate of a transistor of the power amplifier, and
the constant supply to bias the drain of the power amplifier based on a selected position of the first supply switch.

2. The amplifier arrangement according to claim 1 , wherein the amplifier arrangement comprises a tunable matching network connected to an output terminal of the amplifier arrangement.

3. The amplifier arrangement according to claim 1 , further comprising:
a constant power supply; and
a second supply switch adapted to select between the constant power supply and the adjustable power supply to bias one or more gates of the power amplifier, the second supply switch controlled by the secondary control signals based on the mode of operation.

4. The amplifier arrangement according to claim 1 , further comprising a tunable matching network connected to an input terminal of the amplifier arrangement to provide a desired matching based on the mode of operation.

5. The amplifier arrangement according to claim 2 , wherein the tunable matching network provides a desired matching based on the mode of operation, and the desired matching is tuned as a function of an envelope signal when the adjustable power supply provides variable supply to the power amplifier.

6. The amplifier arrangement according to claim 1 , further comprising a feedback loop, the feedback loop is connected between an input and an output of the amplifier arrangement and is adapted to adjust an amplitude and/or a phase response of the amplifier arrangement based on the mode of operation.

7. The amplifier arrangement according to claim 6 , wherein the feedback loop comprises a resistor, a capacitor and a feedback loop switch, the feedback loop switch adapted to enable/disable an operation of the feedback loop with respect to the amplifier arrangement and is controlled by secondary control signals based on the mode of operation.

8. The amplifier arrangement according to claim 6 , wherein the feedback loop comprises a tunable resistor and a tunable capacitor, the tunable resistor and the tunable capacitor adapted to tune the feedback loop with respect to the amplifier arrangement and controlled by secondary control signals based on the mode of operation.

9. The amplifier arrangement according to claim 1 , wherein the bias voltages to the one or more gates of the power amplifier is provided from an external power supply.

10. The amplifier arrangement according to claim 1 , further comprising one or more voltage divider resistors in series connection with the adjustable power supply, the one or more voltage divider resistors adapted to generate a proportioned bias voltage to one or more gates of the power amplifier.

11. The amplifier arrangement according to claim 1 , further comprising one or more bias terminal supply switches, wherein the bias terminal supply switches are connected to one or more gate bias terminals of the power amplifier and are adapted to select between providing one or more gate bias terminals with bias voltages from either an external power supply or the adjustable power supply, the one or more bias terminal supply switches controllable by secondary control signals based on the mode of operation.

12. The amplifier arrangement according to claim 1 , wherein the amplifier arrangement further comprises:
an envelope detector operative to receive an input RF signal and configured to provide as an output an envelope signal corresponding to an envelope of the input RF signal; and
a control unit connected with the envelope detector, the control unit operative to receive the envelope signal from the envelope detector and configured to generate the first control signal.

13. The amplifier arrangement according to claim 12 , wherein the control unit is further configured to provide secondary control signals to the power amplifier, wherein the secondary control signal further configures the power amplifier through the configuring arrangement based on the mode of operation.

14. The amplifier arrangement according to claim 12 , wherein a secondary control signal is provided to the amplifier arrangement not by the control unit.

15. The amplifier arrangement according to claim 14 , wherein the secondary control signal is provided to the amplifier arrangement from a transceiver.

16. The amplifier arrangement according to claim 13 , wherein the configuring arrangement comprises switches and/or tunable elements used to configure the operation of the power amplifier based on the mode of operation.

17. The amplifier arrangement according to claim 1 further comprising a second plurality of stacked FET transistors, wherein the second plurality of stacked FET transistors comprises a number of stacked FET transistors different from a first plurality of stacked FET transistors of the power amplifier; and
a stack switch connected to the adjustable power supply and operative to select between the first plurality of stacked FET transistors or the second plurality of stacked FET transistors, the stack switch is controlled by secondary control signals based on the mode of operation.

18. The amplifier arrangement according to claim 13 , wherein the configuring arrangement is adapted to perform one or more of: a) configuring a bias voltage to a gate of at least one of the one or more gates, and b) activating and/or deactivating at least one of a plurality of stacked FET transistors of the power amplifier.

19. The amplifier arrangement of claim 1 , wherein the mode of operation is based on a combination of: a) a power consumption of the adjustable power supply, b) a power level of an input signal to the amplifier arrangement, and c) a power level of an output signal of the amplifier arrangement.

20. The amplifier according to claim 1 , wherein the first mode of operation comprises one of: a) envelope tracking, b) envelope following, c) average power tracking, and d) polar modulation.

21. The amplifier arrangement according to claim 16 , wherein the tunable elements comprise at least one tunable capacitor and one tunable resistor operatively connected to a gate of the one or more gates of the power amplifier, the tunable capacitor being connected between the gate and a reference voltage, and the tunable resistor being series connected between the gate and a corresponding bias voltage terminal.

22. The amplifier arrangement ac

Assignees

• Psemi Corp

Inventors

• Nobbe Dan William
• Dykstra Jeffrey A
• Olson Chris
• Cable James S

Classifications

• H03F2200/411

  the output amplifying stage of an amplifier comprising two power stages · CPC title

• H03F3/45188

  Non-folded cascode stages · CPC title

• H03F1/3247

  using feedback acting on predistortion circuits (H03F1/3264 takes precedence) · CPC title

• H03F1/025

  by using a signal derived from the input signal · CPC title

• H03F2200/18

  the bias of the gate of a FET being controlled by a control signal · CPC title