Amplifier dynamic bias adjustment for envelope tracking

Patent metadata

Field	Value
Publication number	US-9973145-B2
Application number	US-201514958848-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Dec 28, 2012
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor.

First claim

The invention claimed is:

1. A circuital arrangement comprising:
an amplifier comprising:
stacked transistors having a plurality of gate terminals configured to operatively provide a plurality of dynamic bias voltages or currents to the stacked transistors;
an input port operatively connected to a gate terminal of an input transistor of the stacked transistors configured to receive a radio frequency (RF) signal;
an output port operatively connected to an output transistor of the stacked transistors configured to output an amplified version of the RF signal; and
a reference terminal operatively coupling the input transistor to a reference potential, wherein the stacked transistors comprise a first subset and a second subset of transistors operatively arranged in series:
a) the first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and the second subset; and
b) the second subset comprises:
i) one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to a drain terminal of the output transistor; and
ii) one or more gate capacitors, each gate capacitor of the one or more gate capacitors connected between a respective gate terminal of each transistor of the one or more transistors of the second subset and the reference potential, wherein the each gate capacitor is configured to allow a gate voltage at the respective gate terminal to vary along with a radio frequency (RF) voltage at a drain of the each transistor.

2. The circuital arrangement according to claim 1 , further comprising a variable voltage or current source operatively coupled to the circuital arrangement and configured to output one or more variable voltages or currents according to a control signal applied to the variable voltage or current source.

3. The circuital arrangement according to claim 2 , wherein the control signal is a function of an envelope signal of an input signal to the amplifier, such as the applying of the control signal impresses said function upon the one or more variable voltages or currents output by the variable voltage or current source.

4. The circuital arrangement according to claim 3 , wherein the amplifier is configured to operate in at least one of: a) linear region, b) compression region, or c) switching between compression and linear regions.

5. The circuital arrangement according to claim 4 , wherein the dynamic bias voltages or currents are operatively generated from a first variable voltage or current of the one or more variable voltages or currents and the variable output supply bias voltage or current is operatively generated from a second variable voltage or current of the one or more variable voltages or currents.

6. The circuital arrangement according to claim 1 , wherein the one or more capacitors are configured to perform any combination of: a) optimize a bias voltage across each of the one or more transistors for a desired operation of the amplifier, b) optimize an envelope signal voltage across each of the one or more transistors for a desired operation of the amplifier, and c) optimize an RF voltage swing across each of the one or more transistors for a desired operation of the amplifier.

7. The circuital arrangement according to claim 1 , further comprising one or more resistors connected in series between the gate terminals of the one more transistors of the second subset and the provided plurality of dynamic bias voltages or currents.

8. The circuital arrangement according to claim 5 further comprising a circuital arrangement connected in series between at least one gate terminal of the one or more transistors of the second subset and the provided plurality of dynamic bias voltages or currents, the circuital arrangement comprising at least one active device.

9. The circuital arrangement according to claim 8 , wherein the circuital arrangement is configured to operate in a frequency range spanning from DC to a frequency content of the input signal.

10. The circuital arrangement according to claim 5 , wherein at least one of the plurality of the dynamic bias voltages or currents is generated from the first variable voltage or current using a gate modifier function, wherein the gate modifier function comprises at least one of: a) a scaling function, b) an amplitude shifting function, c) a phase shifting function, and d) an inverting function.

11. The circuital arrangement according to claim 10 further comprising a gate modifier circuital arrangement to generate said gate modifier function, wherein the gate modifier circuital arrangement comprises at least one of: a) a resistive-inductive-capacitive (RLC) network, b) a current mirror, c) one or more operational amplifiers, and d) one or more digital integrated circuits.

12. The circuital arrangement according to claim 11 , wherein the first variable voltage or current is different from the second variable voltage or current.

13. The circuital arrangement according to claim 11 , wherein the first variable voltage or current is the same as the second variable voltage or current.

14. The circuital arrangement according to claim 12 , wherein the gate terminal of the input transistor is adapted to receive a bias input gate voltage or current which is not generated from the first or the second variable voltage or current.

15. The circuital arrangement according to claim 13 , wherein the gate terminal of the input transistor is adapted to receive a bias input gate voltage or current which is not generated from the first or the second variable voltage or current.

16. The circuital arrangement according to claim 5 , wherein the gate terminal of the input transistor is adapted to receive a bias input gate voltage or current which is not generated from the first or the second variable voltage or current.

17. The circuital arrangement according to claim 5 , further comprising an inductor configured as a choke operatively connected between the output transistor and the variable output supply bias voltage or current provided to the output transistor.

18. The circuital arrangement according to claim 5 , wherein the variable voltage or current source is a DC-DC converter.

19. The circuital arrangement according to claim 5 , wherein the variable voltage or current source is a DC-DC converter and a linear regulator operatively connected in parallel or in series with each other.

20. The circuital arrangement according to claim 5 , wherein the variable voltage or current source is operatively coupled to the drain terminal of the output transistor and is adapted to vary a voltage of the variable output supply bias voltage or current.

21. The circuital arrangement according to claim 5 , wherein the variable voltage or current source is operatively coupled to a source terminal of the input transistor and is adapted to vary a current of the variable output supply bias voltage or current.

22. The circuital arrangement according to claim 5 , wherein a direct current (DC) component of an at least one of the plurality of the dynamic bias voltages or currents is not operatively generated from the first variable voltage or current.

23. The circuital arrangement according to claim 5 , wherein the stacked transistors are configured in a cascode co

Assignees

• Psemi Corp

Inventors

• Nobbe Dan William
• Dykstra Jeffrey A
• Olson Chris
• Cable James S

Classifications

• H03F1/0244

  Stepped control · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H03F2200/411

  the output amplifying stage of an amplifier comprising two power stages · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H03F2203/45112

  the biasing of the differential amplifier being controlled from the input or the output signal · CPC title