Bias control for stacked transistor configuration

Patent metadata

Field	Value
Publication number	US-9716477-B2
Application number	US-201514626833-A
Country	US
Kind code	B2
Filing date	Feb 19, 2015
Priority date	Dec 28, 2012
Publication date	Jul 25, 2017
Grant date	Jul 25, 2017

Abstract

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.

First claim

The invention claimed is:

1. A circuital arrangement comprising:
i) an amplifier comprising:
stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;
an input port operatively connected to an input transistor of the stacked transistors;
an output port operatively connected to the drain terminal of the output transistor; and
a reference terminal operatively coupling the input transistor to a reference potential,
wherein:
the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor, the variable output supply bias voltage or current being based on an envelope signal of an RF signal at the input port; and

ii) a gate bias circuit,
wherein:
the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a voltage at a source terminal of the each transistor, the gate DC offset voltage being based on a gate-to-source voltage of the each transistor, and the voltage at the source terminal of the each transistor being based on a distribution of a voltage at the drain terminal of the output transistor across the stacked transistors.

2. The circuital arrangement according to claim 1 , wherein the voltage at the drain terminal of the output transistor is based on the variable output supply bias voltage or current provided to the output transistor.

3. The circuital arrangement according to claim 1 , further comprising one or more gate capacitors connected between the gate terminals of the one or more transistors of the second subset and the reference potential.

4. The circuital arrangement according to claim 3 , wherein capacitance values of the one or more gate capacitors are based on an operating frequency of an RF signal at the input port.

5. The circuital arrangement according to any one of claims 1 - 3 , wherein the distribution is an equal distribution of the voltage at the drain terminal of the output transistor across the stacked transistors.

6. The circuital arrangement according to any one of claims 1 - 3 , wherein the distribution provides a voltage across the output transistor which is higher than a voltage across other transistors of the stacked transistors.

7. The circuital arrangement according to any one of claims 1 - 3 , wherein the distribution provides a voltage across the input transistor which is higher than a voltage across other transistors of the stacked transistors.

8. The circuital arrangement according to any one of claims 1 - 3 , wherein the gate DC offset voltage is one or a fraction of the gate-to-source voltage of the each transistor.

9. The circuital arrangement according to any one of claims 1 - 3 , further comprising a filter configured to provide at the gate terminal of each transistor of the one or more transistors of the second subset a filtered bias voltage based on a filtered version of the variable output supply bias voltage or current, wherein a voltage at the gate terminal of the each transistor is the sum of the filtered bias voltage and the dynamic bias voltage.

10. The circuital arrangement according to claim 9 , wherein a cutoff frequency of the filter is based on a geometric mean of an operating frequency of an RF signal at the input port and an upper frequency of the variable supply bias voltage or current.

11. The circuital arrangement according to claim 10 , wherein the operating frequency is about 700 MHz, the upper frequency of the variable supply bias voltage or current is about 30 MHz and the cutoff frequency is about 145 MHz.

12. The circuital arrangement according to claim 10 , wherein the filter is one of: a) a low pass filter, b) a pass band filter, and c) a band reject filter.

13. The circuital arrangement according to claim 9 , wherein the further circuitry comprises one or more series connected resistive-capacitive (RC) networks operatively coupled between gate terminals of the one or more transistors of the one or more transistors of the second subset and the variable output supply bias voltage or current.

14. A circuital arrangement comprising:
i) an amplifier comprising:
stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;
an input port operatively connected to an input transistor of the stacked transistors;
an output port operatively connected to the drain terminal of the output transistor; and
a reference terminal operatively coupling the input transistor to a reference potential,
wherein:
the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor; and

ii) a gate bias circuit configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a voltage at a source terminal of the each transistor, the gate DC offset voltage being based on a gate-to-source voltage of the each transistor, and the voltage at the source terminal of the each transistor being based on a distribution of a voltage at the drain terminal of the output transistor across the stacked transistors, the gate bias circuit comprising:
a resistor voltage divider operatively coupled between the variable output supply bias voltage or current and the reference potential, wherein nodes of the resistor voltage divider are coupled to the gate terminal of the each transistor of the one or more transistors of the second subset; and
one or more current sources operatively coupled to one or more nodes of the resistor voltage divider,

wherein:
the resistor voltage divider provides voltages at the gate terminals of the each transistor of the one or more transistors of the second subset which are based on the distribution of the voltage at the drain terminal of the output transistor, and
the one or more current sources provide the gate DC offset voltage at the gate terminal of the each transistor of the one or more transistors of the second subset.

15. The circuital arrangement according to claim 14 , wherein nodes of the resistor voltage divider are coupled to the gate terminal of the each transistor via a series connected resistor.

16. The circuital arrangement according to claim 14 , wherein nodes of the resistor voltage divider further comprise capacitance to provide low filtering of the voltages provided by

Assignees

• Peregrine Semiconductor Corp

Inventors

• Wagh Poojan
• Golat Joseph
• Kovac David
• Dykstra Jeffrey A
• Olson Chris

Classifications

• H03F2203/45638

  the LC comprising one or more coils · CPC title

• H03F1/0227

  using supply converters · CPC title

• H03F2203/45544

  the IC comprising one or more capacitors, e.g. coupling capacitors · CPC title

• H03F2201/3233

  Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title