Vertical transport transistors with equal gate stack thicknesses

Patent metadata

Field	Value
Publication number	US-10157923-B2
Application number	US-201715806759-A
Country	US
Kind code	B2
Filing date	Nov 8, 2017
Priority date	May 1, 2017
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

Methods of forming semiconductor devices include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.

First claim

What is claimed is:

1. A method for forming semiconductor devices, comprising:
forming a bottom source/drain layer;
forming vertical semiconductor channels on the bottom source/drain layer in a first-type region and a second-type region after forming the bottom source/drain layer;
forming a gate dielectric layer on sidewalls of the vertical semiconductor channels;
forming a first-type work function layer in the first-type region;
forming a second-type work function layer in both the first-type region and the second-type region;
forming a thickness matching layer in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region; and
forming top source/drain regions on a top portion of the vertical channels.

2. The method of claim 1 , further comprising forming a scavenging layer over the second-type work function layer.

3. The method of claim 1 , wherein a portion of the first-type work function layer and the second-type work function layer in an area between the first-type region and the second-type region is preserved.

4. The method of claim 1 , further comprising recessing a first-type stack, formed from the first-type work function layer and the second-type work function layer, and a second-type stack, formed from the second-type work function layer and the thickness matching layer, below a height of the vertical semiconductor channels.

5. The method of claim 4 , further comprising forming spacers on exposed sidewalls of the vertical semiconductor channels.

6. The method of claim 5 , further comprising etching away a portion of the first-type work function layer and the second-type work function layer from an area between the first-type region and the second-type region.

7. The method of claim 5 , further comprising etching back the spacers before forming the top source/drain regions.

8. The method of claim 1 , wherein the thickness matching layer comprises titanium nitride.

9. The method of claim 1 , wherein the thickness matching layer comprises a material selected from the group consisting of cobalt and tungsten.

10. A method for forming semiconductor devices, comprising:
forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region;
forming a gate dielectric layer on sidewalls of the vertical semiconductor channels;
forming a first-type work function layer in the first-type region;
forming a second-type work function layer in both the first-type region and the second-type region;
further comprising forming a scavenging layer over the second-type work function layer;
forming a thickness matching layer in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region; and
forming top source/drain regions on a top portion of the vertical channels.

11. The method of claim 10 , wherein a portion of the first-type work function layer and the second-type work function layer in an area between the first-type region and the second-type region is preserved.

12. The method of claim 10 , further comprising recessing a first-type stack, formed from the first-type work function layer and the second-type work function layer, and a second-type stack, formed from the second-type work function layer and the thickness matching layer, below a height of the vertical semiconductor channels.

13. The method of claim 12 , further comprising forming spacers on exposed sidewalls of the vertical semiconductor channels.

14. The method of claim 13 , further comprising etching away a portion of the first-type work function layer and the second-type work function layer from an area between the first-type region and the second-type region.

15. The method of claim 13 , further comprising etching back the spacers before forming the top source/drain regions.

16. A method for forming semiconductor devices, comprising:
forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region;
forming a gate dielectric layer on sidewalls of the vertical semiconductor channels;
forming a first-type work function layer in the first-type region;
forming a second-type work function layer in both the first-type region and the second-type region;
forming a thickness matching layer in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region;
recessing a first-type stack, formed from the first-type work function layer and the second-type work function layer, and a second-type stack, formed from the second-type work function layer and the thickness matching layer, below a height of the vertical semiconductor channels;
forming spacers on exposed sidewalls of the vertical semiconductor channels; and
forming top source/drain regions on a top portion of the vertical semiconductor channels.

17. The method of claim 16 , further comprising forming a scavenging layer over the second-type work function layer.

18. The method of claim 16 , wherein a portion of the first-type work function layer and the second-type work function layer in an area between the first-type region and the second-type region is preserved.

19. The method of claim 1 , wherein the second-type work function layer is formed over the first-type work function layer in the first-type region and wherein the thickness matching layer is formed on the second-type work function layer.

Assignees

• IBM

Inventors

• Bao Ruqiang
• Bi Zhenxing
• Lee Choonghyun
• Xu Zheng

Classifications

• H01L29/78642

  Electricity · mapped topic

• H01L29/66719

  Electricity · mapped topic

• H01L27/092 Primary

  Electricity · mapped topic

• H01L29/7803

  Electricity · mapped topic

• H01L27/0664

  Electricity · mapped topic