Semiconductor structure having layer with re-entrant profile and method of forming the same

Patent metadata

Field	Value
Publication number	US-10157773-B1
Application number	US-201715823687-A
Country	US
Kind code	B1
Filing date	Nov 28, 2017
Priority date	Nov 28, 2017
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A method of forming a semiconductor structure is provided. In this method, a semiconductor substrate is provided. A SoC layer is formed on the semiconductor substrate. A hard mask layer is formed over the SoC layer. The hard mask layer is patterned to expose a portion of the SoC layer. At least one opening is formed on the portion of the SoC layer using an ALE operation, thereby enabling the remaining portion of the SoC layer adjacent to the at least one opening to have a re-entrant angle included between a sidewall of the SoC layer and a bottom of the SoC layer.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, the method comprising:
providing a semiconductor substrate;
forming a spin-on carbon (SoC) layer on the semiconductor substrate;
forming a hard mask layer over the SoC layer;
patterning the hard mask layer to expose a portion of the SoC layer; and
forming at least one opening on the portion of the SoC layer using an atomic layer etching (ALE) operation, thereby enabling the remaining portion of the SoC layer adjacent to the at least one opening to have a re-entrant angle included between a sidewall of the SoC layer and a bottom of the SoC layer, the ALE operation comprising:
performing a first cycle of an etching operation on the portion of the SoC layer, the first cycle of the etching operation including:
flowing a passivation gas over the portion of the SoC layer at a first flow rate F1 and an etching gas over the portion of the SoC layer at a second flow rate F2 under a first pressure P1; and
performing an ionized noble gas bombardment on the portion of the SoC layer at a first temperature T1;
performing a second cycle of the etching operation on the portion of the SoC layer, the second cycle of the etching operation including:
flowing the passivation gas over the portion of the SoC layer at a third flow rate F3 and the etching gas over the portion of the SoC layer at a fourth flow rate F4 under a second pressure P2; and
performing the ionized noble gas bombardment on the portion of the SoC layer at a second temperature T2; and
performing a third cycle of the etching operation on the portion of the SoC layer, the third cycle of the etching operation including:
flowing the passivation gas over the portion of the SoC layer at a fifth flow rate F5 and the etching gas over the portion of the SoC layer at a sixth flow rate F6 under a third pressure P3; and
performing the ionized noble gas bombardment on the portion of the SoC layer at a third temperature T3,
wherein the ALE operation satisfies the following relationships:
P1<P2<P3; F1>F3>F5; F2<F4<F6; and T1<T2<T3.

2. The method of claim 1 , wherein the hard mask layer comprises a first hard mask layer and a second hard mask layer on the first hard mask layer.

3. The method of claim 2 , wherein the first hard mask layer comprises an oxide layer, and the second hard mask layer comprises a nitride layer.

4. The method of claim 1 , wherein the re-entrant angle is greater than 90°.

5. The method of claim 1 , wherein after the third cycle of the etching operation, the ALE operation further comprises one or more cycles of the etching operation, and each cycle has a lower passivation gas flow rate, a higher etching gas flow rate, a higher temperature and a higher pressure than those in a cycle prior thereto.

6. The method of claim 1 , wherein the passivation gas comprises a hydrocarbon gas or a sulfur-containing gas, and the etching gas is a mixture of a N 2 and H 2 -based gas.

7. The method of claim 1 , wherein the first pressure P1, the second pressure P2 and the third pressure P3 are in a range substantially from 3 mtorr to 800 mtorr, and the first temperature T1, the second temperature T2 and the third temperature T3 are in a range substantially from 0° C. to 100° C.

8. The method of claim 1 , wherein a temperature difference between the first temperature T1 and the second temperature T2, and/or between the second temperature T2 and the third temperature T3 is at least 5° C.

9. The method of claim 1 , wherein after the ionized noble gas bombardment, each of the first cycle of the etching operation, the second cycle of the etching operation and/or the third cycle of the etching operation comprises performing a desorption operation on the portion of the SoC layer.

10. The method of claim 1 , wherein the first pressure P1 is not higher than 20 mtorr.

11. A method of forming a semiconductor structure, the method comprising:
providing a semiconductor substrate;
forming a SoC layer on the semiconductor substrate;
forming a hard mask layer over the SoC layer;
patterning the hard mask layer to expose a portion of the SoC layer;
performing an ALE operation on the portion of the SoC layer, thereby forming at least one opening on the portion of the SoC layer, wherein the ALE operation comprises a first cycle, a second cycle and a third cycle of an etching operation, wherein each of the cycles includes operations of flowing a passivation gas and an etching gas over the portion of the SoC layer and performing an ionized noble gas bombardment on the portion of the SoC layer, and wherein with sequential processing of the first, second and third cycles, a flow rate of the passivation gas decreases, a flow rate of the etching gas increases, a pressure in the operation of flowing each of the gases increases, and a temperature in the operation of performing the ionized noble gas bombardment increases;
filling the at least one opening with a dielectric material;
removing a remaining portion of the SoC layer, thereby forming at least one metal-filling space, wherein a re-entrant angle is included between a bottom of the at least one metal-filling space and a sidewall of the at least one metal-filling space; and
filling the at least one metal-filling space with a metal material.

12. The method of claim 11 , wherein removing the remaining portion of the SoC layer comprises performing an ash process on the remaining portion of the SoC layer.

13. The method of claim 11 , wherein the passivation gas comprises a hydrocarbon gas or a sulfur-containing gas, and the etching gas is a mixture of a N 2 and H 2 -based gas.

14. The method of claim 11 , wherein the pressure is in a range substantially from 3 mtorr to substantially 800 mtorr, and the temperature is in a range substantially from 0° C. to 100° C.

15. The method of claim 11 , wherein the ALE operation comprises a plurality of the first cycles, a plurality of the second cycles and/or a plurality of the third cycles.

16. The method of claim 15 , wherein the second cycles are performed after all of the first cycles are finished, and the third cycles are performed after all of the second cycles are finished.

17. The method of claim 11 , wherein after the third cycle of the etching operation, the ALE operation further comprises one or more cycles of the etching operation, and each of the one or more cycles of the etching operation has a lower passivation gas flow rate, a higher etching gas flow rate, a higher temperature and a higher pressure than those in its previous cycle respectively.

18. The method of claim 11 , wherein the re-entrant angle is greater than 90°.

19. An etching method, comprising:
providing a semiconductor substrate on which a SoC layer and a hard mask layer are formed, wherein a portion of the SoC layer is exposed from the hard mask layer;
performing an etching operation to form at least one opening on the portion of the SoC layer, wherein the etching operation comprises:
flowing a passivation gas at a first passivation gas flow rate and an etching gas at a first etching gas flow rate over the portion of the SoC layer at a first pressure and performing an ionized noble gas bombardment on the portion of the SoC layer for a vertical-dominant etching operation; and
flowing the passivation gas at a second passivation gas flow rate and the etching gas at a second etching gas flow rate over the portion of the SoC layer at a second pressure and performing the ionized noble gas bombardment on the portion of the SoC layer for a lateral-dominant etching oper

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Yi-Shan
• Yang Chan-Syun David
• Lin Li-Te
• Lin Pinyen

Classifications

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P14/6902

  composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon · CPC title

• H10P14/6342

  Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P76/403

  for lift-off processes · CPC title