Integrated circuit with an amplifier MOSFET

Patent metadata

Field	Value
Publication number	US-10156864-B2
Application number	US-201715679263-A
Country	US
Kind code	B2
Filing date	Aug 17, 2017
Priority date	Aug 17, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

In accordance with an embodiment, an integrated circuit includes a substrate, an amplifier MOSFET, and a bias voltage terminal configured to generate a potential difference of the substrate relative to at least one load terminal of the amplifier MOSFET.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate;
an amplifier MOSFET; and
a bias voltage terminal configured to generate a potential difference of the substrate relative to at least one load terminal of the amplifier MOSFET, wherein a resistivity of the substrate is not less than 0.3 kohm cm, and the potential difference is −3 volts or more negative.

2. The integrated circuit as claimed in claim 1 , wherein a gate width of the amplifier MOSFET is greater than 100 μm.

3. The integrated circuit as claimed in claim 1 , wherein the resistivity and the potential difference are bulk properties of the substrate in a region of the integrated circuit.

4. The integrated circuit as claimed in claim 1 , further comprising:
at least one input terminal which is connected to a control terminal of the amplifier MOSFET and which is configured to receive at least one input signal, and
an output terminal, which is arranged on a side facing the at least one load terminal of the amplifier MOSFET and which is configured to output an output signal.

5. The integrated circuit as claimed in claim 4 , further comprising: an inductance arranged on the side facing the load terminal of the amplifier MOSFET, wherein the amplifier MOSFET and the inductance are configured to implement a gain factor of the output signal relative to the at least one input signal of not less than 10 dB.

6. The integrated circuit as claimed in claim 4 , further comprising at least one cascode MOSFET arranged between the at least one load terminal of the amplifier MOSFET and the output terminal, wherein the at least one cascode MOSFET and the amplifier MOSFET have a same gate length.

7. The integrated circuit as claimed in claim 4 , further comprising at least one switch arranged adjacent to the at least one input terminal, the at least one switch comprising a series connection of switch MOSFETs coupled to a ground connection, wherein the switch MOSFETs and the amplifier MOSFET have a same gate length.

8. The integrated circuit as claimed in claim 7 , wherein the at least one switch is arranged in a bypass branch, wherein the bypass branch connects the at least one input terminal to the output terminal whilst bypassing the amplifier MOSFET.

9. The integrated circuit as claimed in claim 7 ,
wherein the integrated circuit comprises a plurality of switches and a plurality of input terminals, and
wherein at least some of the plurality of switches are associated in each case with a corresponding one of the plurality of input terminals.

10. The integrated circuit as claimed in claim 7 , further comprising at least one overvoltage protection element having at least one ESD MOSFET, wherein the at least one ESD MOSFET and the amplifier MOSFET have a same gate length, wherein the at least one overvoltage protection element is implemented by the at least one switch.

11. The integrated circuit as claimed in claim 7 , further comprising at least one overvoltage protection element having at least one ESD MOSFET,
wherein the at least one overvoltage protection element is arranged between the at least one load terminal of the amplifier MOSFET and the output terminal.

12. The integrated circuit as claimed in claim 1 , wherein the resistivity of the substrate is not less than 0.5 kohm cm.

13. The integrated circuit as claimed in claim 1 , wherein the potential difference is −4 volts or more negative.

14. The integrated circuit as claimed in claim 1 , wherein the at least one load terminal of the amplifier MOSFET is arranged using bulk technology in relation to the substrate.

15. The integrated circuit as claimed in claim 1 , wherein the substrate is a silicon substrate.

16. The integrated circuit as claimed in claim 1 , wherein the amplifier MOSFET implements a low noise amplifier or a power amplifier.

17. An analog output stage of a radio-frequency transceiver, comprising:
an antenna, and
an integrated circuit comprising
a substrate,
an amplifier MOSFET, and
a bias voltage terminal configured to generate a potential difference of the substrate relative to at least one load terminal of the amplifier MOSFET, wherein a resistivity of the substrate is not less than 0.3 kohm cm, and the potential difference is 3 volts or more negative, wherein the antenna is connected to an input terminal of the integrated circuit.

18. A method comprising:
processing a substrate having a resistivity of not less than 0.3 kohm cm; and
providing an integrated circuit on the substrate, said integrated circuit comprising an amplifier MOSFET and a bias voltage terminal, wherein the bias voltage terminal is configured to generate a potential difference of the substrate relative to at least one load terminal of the amplifier MOSFET, which potential difference is −3 volts or more negative.

Assignees

• Infineon Technologies Ag

Inventors

• Bakalski Winfried
• Simbuerger Werner
• Steltenpohl Anton
• Taddiken Hans

Classifications

• H03G1/007

  using field-effect transistors [FET] · CPC title

• H01L29/1029

  Electricity · mapped topic

• H01L27/0922

  Electricity · mapped topic

• H01L27/0629

  Electricity · mapped topic

• H03G1/0029

  using field-effect transistors [FET] · CPC title