Integrated antenna structure and array

Patent metadata

Field	Value
Publication number	US-9305888-B2
Application number	US-201414287338-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	Jul 5, 2012
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

Some embodiments relate to a semiconductor module having an integrated antenna structure that wirelessly transmits signals. The semiconductor module has a first die having a first far-back-end-of-the-line (FBEOL) metal layer with a ground plane connected to a ground terminal. A second die is stacked onto the first die and has a second FBEOL metal layer with an antenna exciting element that extends to a position that is vertically over the ground plane. One or more micro-bumps are vertically located between the first FBEOL metal layer and the second FBEOL metal layer. The one or more micro-bumps provide a radio frequency (RF) signal between the first FBEOL metal layer and the antenna exciting element of the second FBEOL metal layer. By using micro-bumps to connect the first and second die, the FBEOL metal layers are separated by a large spacing that provides for good performance of the integrated antenna structure.

First claim

What is claimed is:

1. A semiconductor module comprising an integrated antenna structure, comprising:
a first die having a first far-back-end-of-the-line (FBEOL) metal layer comprising a ground plane connected to a ground terminal;
a second die stacked onto the first die and having a second FBEOL metal layer comprising an antenna exciting element that extends to a position that is vertically over the ground plane; and
one or more micro-bumps vertically disposed between the first FBEOL metal layer and the second FBEOL metal layer and laterally offset from the ground plane.

2. The semiconductor module of claim 1 , wherein the second die further comprises:
a through-silicon-via (TSV) extending through the second die and providing an electrical connection between the first FBEOL metal layer and the second FBEOL metal layer, which is disposed on a back-side of the second die that opposes the first die.

3. The semiconductor module of claim 1 ,
wherein the ground plane comprises the first FBEOL metal layer and the second FBEOL metal layer, which is disposed onto a front-side side of the second die that faces the first die; and
wherein the antenna exciting element comprises the first FBEOL metal layer and the second FBEOL metal layer.

4. The semiconductor module of claim 1 , wherein the antenna exciting element is disposed onto a front-side of the second die that faces the first die.

5. The semiconductor module of claim 1 , wherein the integrated antenna structure is disposed within a first layer of integrated antennas comprising a first plurality of integrated antenna structures disposed in a first two-dimensional antenna array located between the first die and the second die, which is vertically stacked onto the first die.

6. The semiconductor module of claim 5 , further comprising:
a second layer of integrated antennas overlying the first layer of integrated antennas and comprising a second plurality of integrated antenna structures disposed in a second two-dimensional antenna array located between a third die stacked onto the second die and a fourth die.

7. The semiconductor module of claim 6 , wherein the second die and the third die comprise a same die.

8. The semiconductor module of claim 6 , wherein the first plurality of integrated antenna structures are laterally aligned with the second plurality of integrated antenna structures along a first direction and a second direction perpendicular to the first direction.

9. The semiconductor module of claim 6 , wherein the first plurality of integrated antenna structures are laterally offset from the second plurality of integrated antenna structures along a first direction or a second direction perpendicular to the first direction.

10. The semiconductor module of claim 9 , wherein the first plurality of integrated antenna structures are laterally disposed between adjacent integrated antenna structures of the second plurality of integrated antenna structures along the first direction and the second direction so as to form a checkerboard pattern in a vertical direction.

11. The semiconductor module of claim 9 , wherein a first number of the first plurality of integrated antenna structures is different than a second number of the second plurality of integrated antenna structures.

12. The semiconductor module of claim 9 ,
wherein the first plurality of integrated antenna structures comprise a second metal layer;
wherein the second plurality of integrated antenna structures comprise a third metal layer overlying the second metal layer; and
wherein the second plurality of integrated antenna structures are interconnected together by way of the second metal layer.

13. A semiconductor module comprising a stacked integrated antenna array, comprising:
a first layer of integrated antennas comprising a first two-dimensional antenna array having a first plurality of integrated antenna structures comprising a first lower metal layer disposed on a first die and a first upper metal layer disposed on a second die stacked onto the first die; and
a second layer of integrated antennas overlying the first layer of integrated antennas and comprising a second two-dimensional antenna array having a second plurality of integrated antenna structures comprising a second lower metal layer disposed on a third die and a second upper metal layer disposed on a fourth die stacked onto the third die.

14. The semiconductor module of claim 13 , further comprising:
a first adhesion layer comprising one or more micro-bumps disposed between the first die and the second die and configured to physically connect the first die to the second die.

15. The semiconductor module of claim 13 , wherein the first plurality of integrated antenna structures are laterally offset from the second plurality of integrated antenna structures along a first direction or a second direction perpendicular to the first direction.

16. The semiconductor module of claim 13 , wherein the first plurality of integrated antenna structures are laterally disposed between adjacent integrated antenna structures of the second plurality of integrated antenna structures so as to form a checkerboard pattern in a vertical direction.

17. The semiconductor module of claim 13 , wherein the second plurality of integrated antenna structures are interconnected together by way of the first upper metal layer.

18. A stacked integrated antenna array, comprising:
a first layer of integrated antennas comprising a first plurality of integrated antenna structures disposed in a first two-dimensional antenna array located between a first die and a second die stacked onto the first die;
a second layer of integrated antennas overlying the first layer of integrated antennas and comprising a second plurality of integrated antenna structures disposed in a second two-dimensional antenna array located between the second die and a third die stacked onto the second die; and
wherein the first plurality of integrated antenna structures are laterally disposed between adjacent integrated antenna structures of the second plurality of integrated antenna structures so as to form a checkerboard pattern in a vertical direction.

19. The stacked integrated antenna array of claim 18 , wherein the first plurality of integrated antenna structures comprises:
a first lower metal layer comprising a ground plane disposed onto the first die; and
a first upper metal layer comprising an antenna exciting element disposed onto the second die at a position that extends above the ground plane.

20. The stacked integrated antenna array of claim 19 , wherein the first plurality of integrated antenna structures further comprises:
an adhesion layer disposed between the first die and the second die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Ho-Hsiang

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/354

  comprising polymers · CPC title