Tuned semiconductor amplifier

Patent metadata

Field	Value
Publication number	US-9806159-B2
Application number	US-201514878952-A
Country	US
Kind code	B2
Filing date	Oct 8, 2015
Priority date	Oct 8, 2015
Publication date	Oct 31, 2017
Grant date	Oct 31, 2017

Abstract

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.

First claim

What is claimed is:

1. A power transistor comprising:
a plurality of semiconductor transistors connected in parallel;
a first capacitive shunt connected to gate contacts of the semiconductor transistors; and
a second capacitive shunt connected to gate contacts of the semiconductor transistors, wherein a peak of a resonance loop for an S 11 scattering-parameter curve determined at an input node that is common to an electrode of the first capacitive shunt and looking toward the power transistor and with the second capacitive shunt disconnected is at a frequency that is approximately twice a target frequency for the power transistor.

2. The power transistor of claim 1 , wherein the plurality of semiconductor transistors comprise a plurality of gallium-nitride transistors integrated onto a die.

3. The power transistor of claim 2 , wherein the first capacitive shunt comprises:
a first bar capacitor having a capacitance between approximately 5 pF and approximately 60 pF; and
a first plurality of bond wires connected between an electrode of the first bar capacitor and gate pads of the plurality of transistors.

4. The power transistor of claim 3 , wherein the second capacitive shunt comprises:
a second bar capacitor having a capacitance between approximately 5 pF and approximately 60 pF; and
a second plurality of bond wires connected between an electrode of the second bar capacitor and the electrode of the first bar capacitor.

5. The power transistor of claim 4 , wherein the first and second plurality of bond wires are formed of gold and are spaced between approximately 100 microns and approximately 500 microns apart.

6. The power transistor of claim 3 , wherein the bond wires are formed of gold and are spaced between approximately 100 microns and approximately 500 microns apart.

7. The power transistor of claim 2 , wherein the plurality of gallium-nitride transistors include a gallium-nitride layer formed over a silicon substrate.

8. The power transistor of claim 7 , further comprising at least one transition layer formed between the silicon substrate and the gallium-nitride layer.

9. The power transistor of claim 2 , wherein the plurality of gallium-nitride transistors are arranged in a linear array.

10. The power transistor of claim 2 , wherein the plurality of gallium-nitride transistors comprise depletion-mode transistors.

11. The power transistor of claim 2 , wherein the plurality of gallium-nitride transistors comprise high-electron-mobility transistors.

12. The power transistor of claim 2 , wherein a drain efficiency at the target frequency is between approximately 50% and approximately 75%.

13. The power transistor of claim 2 , wherein the plurality of gallium-nitride transistors are arranged in a linear array and a power rating per unit length for the power transistor is between approximately 1 W/mm and approximately 15 W/mm.

14. The power transistor of claim 1 , further comprising:
a package housing the power transistor and the first and second capacitive shunts; and
a metal lead connected to the second capacitive shunt providing a gate connection to the at least one gate contact.

15. The power transistor of claim 14 , wherein a real input impedance for the power transistor is between 0 ohms and approximately 100 ohms.

16. The power transistor of claim 1 , wherein the target frequency is between approximately 1 GHz and approximately 6 GHz.

17. The power transistor of claim 1 , further comprising an output matching network connected to one or more drain pads of the power transistor.

18. The power transistor of claim 1 , further comprising at least one additional passive device connected in an input matching network that includes the first and second capacitive shunts.

19. A method for making at least one power transistor having a two-capacitor input network, the method comprising:
altering a value of a first capacitor in a first capacitive shunt to obtain a first capacitor value at which a resonance loop of an S 11 scattering-parameter curve at an input node that is common to an electrode of the first capacitor and looking toward the power transistor has a peak at a frequency that is approximately twice a target frequency for the power transistor, wherein the first capacitive shunt is connected to at least one gate contact of the power transistor;
adding a second capacitive shunt that is connected to at least one gate contact of the power transistor;
altering a value of a second capacitor in the second capacitive shunt to obtain a second capacitive value at which an input impedance at an input to the second capacitive shunt is approximately equal to a target impedance value; and
making at least one power transistor having a first capacitor with the first capacitor value and a second capacitor with the second capacitor value in the two-capacitor input network.

20. The method of claim 19 , further comprising connecting an electrode of the second capacitor to an electrode of the first capacitor with a plurality of bond wires.

21. The method of claim 20 , further comprising connecting the electrode of the second capacitor to a package gate lead.

22. The method of claim 20 , wherein the second capacitor is a bar capacitor.

23. The method of claim 19 , further comprising connecting an electrode of the first capacitor to gate pads of the power transistor with a plurality of bond wire connections.

24. The method of claim 23 , wherein the first capacitor is a bar capacitor.

25. The method of claim 19 , wherein the power transistor comprises gallium nitride in an active region of the transistor.

26. The method of claim 19 , wherein the target frequency is between approximately 1 GHz and approximately 6 GHz.

27. The method of claim 19 , wherein altering the value of the first capacitor comprises selecting a value of the first capacitor in a range between approximately 5 pF and approximately 60 pF.

28. The method of claim 19 , wherein altering the value of the second capacitor comprises selecting a value of the second capacitor in a range between approximately 5 pF and approximately 60 pF.

29. The method of claim 19 , further comprising an output matching network connected to one or more drain pads of the power transistor.

30. The method of claim 19 , wherein the S 11 scattering-parameter curve is determined by numerical simulation.

31. The method of claim 19 , wherein the S 11 scattering-parameter curve includes the effect of gate-to-source capacitance (C gs ).

32. The method of claim 19 , wherein the target impedance value comprises between 0 ohms and 100 ohms of real impedance.

33. The method of claim 19 , wherein the power transistor comprises one or more depletion-mode transistors disposed in a linear array on a semiconductor die.

34. The method of claim 19 , further comprising:
selecting a first value for the first capacitor;
selecting a second value for the second capacitor; and
assembling the power transistor in a package with a first capacitor having the first value and a second capacitor having the second value.

Assignees

• M/A-Com Tech Solutions Holdings Inc
• Macom Tech Solutions Holdings Inc

Inventors

• Nagy Walter H
• Pattison Lyndon

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/5453

  connecting between multiple bond pads on a chip, e.g. daisy chain · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/555

  of outermost layers of multilayered bond wires, e.g. material of a coating · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title