Package-bottom through-mold via interposers for land-side configured devices for system-in-package apparatus

Patent metadata

Field	Value
Publication number	US-10153253-B2
Application number	US-201615357233-A
Country	US
Kind code	B2
Filing date	Nov 21, 2016
Priority date	Nov 21, 2016
Publication date	Dec 11, 2018
Grant date	Dec 11, 2018

Abstract

A system-in-package apparatus includes a package substrate configured to carry at least one semiconductive device on a die side and a through-mold via package bottom interposer disposed on the package substrate on a land side. A land side board mates with the through-mold via package bottom interposer, and enough vertical space is created by the through-mold via package bottom interposer to allow space for at least one device disposed on the package substrate on the land side.

First claim

The invention claimed is:

1. A system-in-package apparatus comprising:
a package substrate configured to carry at least one semiconductive device on a die side;
a through-mold via package bottom interposer disposed on the package substrate on a land side, wherein the through-mold via package bottom interposer includes at least one through-mold via;
a land side hoard onto which the through-mold via package bottom interposer is mounted, wherein a hump is disposed on the land side board and couples the through-mold via with a bond pad there between;
at least one device disposed on the package substrate on the land side; and
wherein the at least one through-mold via couples the package substrate and the land side board by a lateral connection, and
a bump array disposed between the through-mold via package bottom interposer and the land side board, wherein the bump array creates a first vertical distance between the through-mold via package bottom interposer and the land side board, wherein the through-mold via package bottom interposer creates a second vertical distance between the bump array and the land side, and wherein second vertical distance is greater than the first vertical distance.

2. The system-in-package apparatus of claim 1 , wherein package substrate is above and on the at least one through-mold via.

3. The system-in-package apparatus of claim 1 , further including at least one fully integrated voltage regulator (FiVR) integrated in the package substrate, wherein the FiVR is disposed below at least one semiconductive device, wherein the at least one semiconductive device is a processor.

4. The system-in-package apparatus of claim 1 , further including at least one fully integrated voltage regulator (FiVR) integrated in the package substrate, wherein the FiVR is disposed below at least one semiconductive device, wherein the at least one semiconductive device is a processor, and wherein the FiVR is located directly below circuitry to facilitate voltage-regulation demand.

5. The system-in-package apparatus of claim 1 , further including at least one fully integrated voltage regulator (FiVR) integrated in the package substrate, wherein the FiVR is disposed below at least one semiconductive device, wherein the at least one semiconductive device is a processor, wherein the FiVR is located directly below circuitry to facilitate voltage-regulation demand, and wherein the FiVR is disposed vertically from a promixate through-mold via.

6. The system-in-package apparatus of claim 1 , wherein the at least one semiconductive device includes a processor and a platform-controller hub, further including:
at least one fully integrated voltage regulator (FiVR) integrated in the package substrate, wherein the FiVR is disposed below the processor.

7. The system-in-package apparatus of claim 1 , wherein the at least one device is a suspended device that is disposed above the land side hoard, and further including a least one landed device disposed on the land side board.

8. The system-in-package apparatus of claim 7 , wherein one device disposed on the land side is an active device and one device disposed on the land side is a passive device.

9. The system-in-package apparatus of claim 1 , wherein the package substrate includes a recess that opens the land side, further including at least one device disposed in the recess.

10. The system-in-package apparatus of claim 1 , further including:
a recess that opens the land side board to a level below the bump array; and
at least one device disposed in the recess.

11. The system-in-package apparatus of claim 1 , further including:
a recess that opens the land side board to a level below the bump array; and
at least one device disposed in the recess, wherein the at least one device has a profile that extends above at least the bump array where the bump array contacts the land side board.

12. The system-in-package apparatus of claim 11 , wherein one device disposed on the land side is an active device and one device disposed on the land side is a passive device.

13. A system-in-package apparatus comprising:
a package substrate configured to carry at least one semiconductive device on a die side;
a through-mold via package bottom interposer disposed on the package substrate on a land side, wherein the through-mold via package bottom interposer includes at least one through-mold via;
a land side board onto which the through-mold via package bottom interposer is mounted, wherein a bump is disposed on the land side board and couples the through-mold via with a bond pad there between;
at least one device disposed on the package substrate on the land side; and
wherein the at least one through-mold via couples the package substrate and the land side board by a lateral connection; and
a bump array disposed between the through-mold via package bottom interposer and the land side board, wherein the bump array creates a first vertical distance between the through-mold via package bottom interposer and the land side hoard, wherein the through-mold via package bottom interposer creates a second vertical distance between the bump array and the land side, wherein second vertical distance is greater than the first vertical distance, and wherein the hump array is spaced apart center-to-center with a third distance of least four bumps spacing that is less than the second distance.

14. The system-in-package apparatus of claim 13 , wherein one device disposed on the land side is an active device and one device disposed on the land side is a passive device.

15. A process of assembling a system-in-package apparatus with a through-mold via package bottom interposer, comprising:
assembling a through-mold via package bottom interposer to a package substrate;
assembling at least one device to the package substrate at an infield that is formed by the through-mold via package bottom interposer; and
assembling the through-mold via package bottom interposer to a land side board by a bump array, wherein the bump array has a first vertical distance, the through-mold via package bottom interposer has a second vertical distance, and wherein the at least one device has a profile that is greater than the second vertical distance.

16. The process of claim 15 , further including:
assembling at least one device to the land side board.

17. The process of claim 15 , wherein assembling the at least one includes assembling a memory die.

18. The process of claim 16 , wherein assembling the at least one device includes assembling a baseband processor.

19. The process of claim 16 , wherein assembling the at least one device; includes assembling a stack of memory dice.

Assignees

• Intel Corp

Inventors

• Loo Howe Yin
• Goh Eng Huat
• Lim Min Suet
• Cheah Bok Eng
• Kong Jackson Chung Peng
• Yong Khang Choong

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title