3D Semiconductor Package Interposer with Die Cavity

Patent metadata

Field	Value
Publication number	US-2016254249-A1
Application number	US-201615154770-A
Country	US
Kind code	A1
Filing date	May 13, 2016
Priority date	Feb 26, 2010
Publication date	Sep 1, 2016
Grant date	—

Abstract

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.

First claim

What is claimed is:

1 . A device, comprising:
a substrate having a top surface; an interposer over the top surface of the substrate and having a first major surface facing the substrate, the interposer having a first redistribution line (RDL) disposed at the first major surface thereof and a second RDL disposed at a second major surface thereof opposite the first major surface; a first integrated circuit die mounted to the second RDL; a second integrated circuit die mounted to the first RDL; an interconnect extending outside a periphery of the interposer, the interconnect electrically connecting the substrate to the first integrated circuit die; a first connector electrically connecting the interposer and the second integrated circuit die; and a second connector electrically connecting the first RDL and the substrate.

2 . The device of claim 1 , further comprising a cavity in the top surface of the substrate, wherein the second integrated circuit die extends into the cavity.

3 . The device of claim 2 , further comprising a thermal pad disposed in the cavity.

4 . The device of claim 1 , wherein the second integrated circuit die comprises a plurality of laterally spaced second integrated circuit dies, the device further comprising:
a cavity in the top surface of the substrate, wherein at least one of the plurality of laterally spaced second integrated circuit dies extends into the cavity, and wherein at least another of the plurality of laterally spaced second integrated circuit dies does not extend into the cavity.

5 . The device of claim 4 , wherein the at least one of the plurality of laterally spaced second integrated circuit dies has a first thickness and the at least another of the plurality of laterally spaced second integrated circuit dies has a second thickness less than the first thickness.

6 . The device of claim 1 , further comprising a heat conductive pad underlying the second integrated circuit die.

7 . The device of claim 1 , wherein the first connector has a first height and the second connector has a second height greater than the first height.

8 . The device of claim 1 , wherein the first connector comprises a conductive bump, and wherein the second connector comprises a post-passivation interconnect structure.

9 . A device, comprising:
a substrate having a top surface; an interposer over the top surface of the substrate, the interposer being connected to the substrate by a first plurality of connectors; a first integrated circuit die connected to a first side of the interposer by a second plurality of connectors; and a second integrated circuit die connected to a second side of the interposer opposite the first side by a third plurality of connectors and connected to the substrate by a fourth plurality of connectors.

10 . The device of claim 9 , further comprising a cavity in a portion of the top surface of the substrate, wherein the first integrated circuit die extends into the cavity.

11 . The device of claim 9 , wherein the interposer comprises a first redistribution layer (RDL) facing the first integrated circuit die, a middle layer, and a second RDL facing the second integrated circuit die, the middle layer separating the first RDL and the second RDL.

12 . The device of claim 9 , wherein ends of the second integrated circuit die extend past edges of the interposer, and wherein the fourth plurality of connectors extend from the ends of the second integrated circuit die to the top surface of the substrate in a line perpendicular to the top surface of the substrate.

13 . The device of claim 9 , further comprising a heat dissipation layer underlying the first integrated circuit die.

14 . The device of claim 9 , wherein the fourth plurality of connectors extend outside a periphery of the interposer.

15 . The device of claim 9 , wherein the first plurality of connectors and the fourth plurality of connectors comprise vertical interconnect structures, and wherein the second plurality of connectors and the third plurality of connectors comprise conductive bumps.

16 . A device, comprising:
a substrate having a top surface; an interposer over the top surface of the substrate, the interposer being connected to the substrate by first interconnects; a first integrated circuit die connected to a first side of the interposer by first connectors; a second integrated circuit die connected to a second side of the interposer opposite the first side by second connectors, the second integrated circuit die having a smaller footprint than the interposer; and a fan-out structure disposed over a top surface of the interposer and extending beyond outermost edges of the interposer, wherein the fan-out structure is electrically connected to second interconnects, the second interconnects in contact with the top surface of the substrate.

17 . The device of claim 16 , further comprising third connectors connecting the fan-out structure to the second integrated circuit die.

18 . The device of claim 16 , further comprising a cavity in the top surface of the substrate, wherein the first integrated circuit die extends into the cavity.

19 . The device of claim 16 , further comprising:
a first molding compound on sidewalls of the interposer, the first interconnects, and the second interconnects; and a second molding compound on the first molding compound, the fan-out structure, and the second integrated circuit die.

20 . The device of claim 16 , wherein the interposer comprises a first redistribution layer (RDL) facing the first integrated circuit die, a middle layer, and a second RDL facing the second integrated circuit die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Jeng Shin-Puu
• Hou Shang-Yun
• Chen Kim Hong
• Hung Wensen
• Huang Szu-Po

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/073

  of die-attach connectors · CPC title