Serial data communications using a UART module and method therefor

Patent metadata

Field	Value
Publication number	US-10148420-B2
Application number	US-201615363929-A
Country	US
Kind code	B2
Filing date	Nov 29, 2016
Priority date	Nov 29, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A data processing system includes a universal asynchronous receive/transmit (UART) module and timer module. The UART module has a first input terminal for receiving an input clock signal, a second input terminal for receiving a receive data signal, and an output terminal for providing a transmit data signal. The receive data signal and the transmit data signal use a baud rate based clock signal determined using the input clock signal, and wherein the output terminal and the second input terminal are coupled together for communicating data with a universal synchronous asynchronous receiver/transmitter (USART) module. The timer module is coupled to receive the input clock signal. The timer module provides a duplicate baud rate clock signal for communication to the USART module. The duplicate baud rate clock signal is substantially the same as the baud rate based clock signal.

First claim

What is claimed is:

1. A data processing system comprising:
a universal asynchronous receive/transmit (UART) module having a first input terminal for receiving an input clock signal, a second input terminal for receiving a receive data signal, and an output terminal for providing a transmit data signal, wherein the receive data signal and the transmit data signal use a baud rate based clock signal determined using the input clock signal, and wherein the output terminal and the second input terminal are coupled together for communicating data with a universal synchronous asynchronous receiver/transmitter (USART) module;
a control register in the UART module having a start bit and a stop bit, and wherein disabling the start bit and the stop bit allows a synchronous USART communication mode between the UART module and the USART module; and
a timer module coupled to receive the input clock signal, the timer module for providing a duplicate baud rate clock signal for being communicated to the USART module, wherein the duplicate baud rate clock signal is substantially the same as the baud rate based clock signal.

2. The data processing system of claim 1 , wherein the baud rate is determined based on the duplicate baud rate clock signal.

3. The data processing system of claim 1 , wherein the data processing system is implemented on an integrated circuit.

4. The data processing system of claim 1 , wherein the UART module communicates data with the USART module in a half-duplex asynchronous USART mode when the start bit and the stop bit are enabled.

5. The data processing system of claim 1 , wherein the UART module further comprises a data reception portion and a data transmission portion, wherein the data reception portion is disabled during data transmission from the UART module, and wherein data transmission portion is disabled during data reception in the UART module.

6. The data processing system of claim 1 , further comprising a coupling element for selectively coupling the second input terminal with the output terminal for operation in the half-duplex asynchronous communication mode, and for selectively decoupling the second input terminal from the output terminal for communication in a UART communication mode.

7. A data processing system comprising:
a universal asynchronous receive/transmit (UART) module having a first input terminal arranged to receive an input clock signal, a second input terminal arranged to receive a receive data signal, and an output terminal arranged to provide a transmit data signal, wherein the receive data signal and the transmit data signal use a baud rate based clock signal determined using the input clock signal, and wherein the output terminal and the second input terminal are coupled together for communicating data with a universal synchronous asynchronous receiver/transmitter (USART) module; and
a timer module coupled to receive the input clock signal, the timer module arranged to provide a duplicate baud rate clock signal for communication to the USART module, wherein the duplicate baud rate clock signal is substantially the same as the baud rate based clock signal, and wherein the UART module may communicate in one of a half-duplex asynchronous USART mode and a synchronous USART communication mode.

8. The date processing system of claim 7 , wherein the UART module further comprises a data reception portion and a data transmission portion, wherein the data reception portion is disabled during data transmission from the UART module, and wherein data transmission portion is disabled during data reception in the UART module.

9. The data processing system of claim 7 , wherein the baud rate is determined based on the duplicate baud rate clock signal.

10. The data processing system of claim 7 , wherein the data processing system is implemented on a single integrated circuit.

11. The data processing system of claim 7 , further comprising a control register in the UART module having a start bit and a stop bit, and wherein disabling the start bit and the stop bit allows the synchronous USART communication mode between the UART module and the USART module.

12. The data processing system of claim 7 , further comprising a coupling element for selectively coupling the second input terminal with the output terminal for operation in the half-duplex asynchronous communication mode, and for selectively decoupling the second input terminal from the output terminal for communication in a UART communication mode.

13. A method for communicating data between a first device having a universal asynchronous receive/transmit (UART) module and a second device having a universal synchronous asynchronous receiver/transmitter (USART) module, the method comprising:
initializing a clock signal for use by the UART module based on the USART module clock frequency;
initializing a baud rate clock for the UART module based on the initialized clock signal;
enabling a half-duplex asynchronous USART mode of the UART module by enabling start and stop bits in a UART control register;
coupling a UART transmit terminal and a UART receive terminal together for communicating with a data terminal of the USART module;
duplicating the baud rate clock for transmission to a clock terminal of the USART module; and
transmitting data between the UART module and the USART module.

14. The method of claim 13 , further comprising enabling a synchronous USART communication mode in the UART module by disabling the start and stop bits in the UART control register.

15. The method of claim 13 , the first device is a data processor.

16. The method of claim 15 , wherein the data processor is implemented on a single integrated circuit.

17. The method of claim 13 , wherein coupling a UART transmit terminal and a UART receive terminal together further comprises using a coupling element to selectively couple the transmit terminal and the UART receive terminal together in response to a control signal.

18. The method of claim 17 , wherein the coupling element is characterized as being a switch.

Assignees

• Nxp Bv

Inventors

• Govind Km Kanal

Classifications

• H04L7/044 Primary

  using a single bit, e.g. start stop bit · CPC title

• H04L5/16

  Half-duplex systems; Simplex/duplex switching; Transmission of break signals {non-automatically inverting the direction of transmission} · CPC title

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title