Dynamic pause period calculation for serial data transmission

Patent metadata

Field	Value
Publication number	US-9753830-B2
Application number	US-201414199785-A
Country	US
Kind code	B2
Filing date	Mar 6, 2014
Priority date	Mar 8, 2013
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A serial transmission peripheral device for transmitting serial transmission data with a variable data length includes a pulse forming unit; and a register programmable to set a desired transmission length. The peripheral device is operable to determine an actual transmission length and calculate a length of a pause pulse and to add the pause pulse at the end of a transmission to generate a transmission having a constant length.

First claim

What is claimed is:

1. A serial transmission peripheral device for transmitting serial transmission data comprising:
a transmitter configured to sequentially transmit a plurality of data nibbles, wherein each data nibble is encoded in a variable length data pulse, and
a register programmable to set a desired transmission length for a plurality of transmission frames each of the plurality of transmission frames including a plurality of sequential variable length data nibble pulses and a pause pulse, wherein the desired transmission length of the transmission frame is a constant pulse width, the constant pulse width not based on a value associated with any one of the plurality of sequential variable length data nibble pulses;
wherein for each transmission frame, the transmitter is configured to calculate a required length of the pause pulse and to add the pause pulse at the end of a transmission of the plurality of sequential variable length data nibble pulses; and
wherein the pause pulse length is computed when a pause period starts.

2. The peripheral device according to claim 1 , further comprising logic configured to perform required addition and subtraction operations in hardware to compute a pause pulse length.

3. The peripheral device according to claim 1 , wherein the pause period is a Single Edge Nibble Transmission protocol pause period.

4. The peripheral device according to claim 1 , wherein each variable length data nibble pulse is transmitted within a pulse period comprising a first period at a first logic level having a fixed length followed by a second period at a second logic level defining the variable length nibble pulse.

5. The peripheral device according to claim 1 , wherein each transmission frame further comprises a synchronization pulse followed by the plurality of sequential variable length data nibble pulses and the pause pulse.

6. The peripheral device according to claim 1 , further comprising a programmable tick period generator generating ticks for controlling a serial transmission signal comprising said transmission frame.

7. A microcontroller, comprising:
a peripheral device including:
a transmitter configured to sequentially transmit a plurality of data nibbles, wherein each data nibble is encoded in a variable length data pulse; and
a register programmable to set a desired transmission length for a plurality of transmission frames each of the plurality of transmission frames comprising a plurality of sequential variable length data nibble pulses and a pause pulse, wherein the desired transmission length of the transmission frame is a constant pulse width, the constant pulse width not based on a value associated with any one of the plurality of sequential variable length data nibble pulses;
wherein for each transmission frame, the transmitter is configured to calculate a required length of the pause pulse and to automatically add the pause pulse at the end of a transmission of the plurality of sequential variable length data nibble pulses; and
wherein the pause pulse length is computed when a pause period starts.

8. The microcontroller according to claim 7 , further comprising logic configured to perform required addition and subtraction operations in hardware to compute a pause pulse length.

9. The microcontroller according to claim 7 , wherein the pause period is a Single Edge Nibble Transmission protocol pause period.

10. The peripheral device according to claim 5 , wherein a first variable length data nibble pulse comprises status information and a last variable length data nibble pulse comprises CRC information.

11. The microcontroller according to claim 7 , wherein each variable length data nibble pulse is transmitted within a pulse period comprising a first period at a first logic level having a fixed length followed by a second period at a second logic level defining the variable length nibble pulse.

12. The peripheral device according to claim 5 , wherein each synchronization pule, variable length data nibble pule and pause pulse is transmitted within a pulse period comprising a first period having a predetermined length at a first logic level followed by a second period at a second logic level.

Assignees

• Microchip Tech Inc

Inventors

• Bowling Stephen
• Naik Samar

Classifications

• H04L7/044

  using a single bit, e.g. start stop bit · CPC title

• H04L25/4902

  Pulse width modulation; Pulse position modulation · CPC title

• H04L7/0091 Primary

  Transmitter details · CPC title

• H04L25/38

  Synchronous or start-stop systems, e.g. for Baudot code · CPC title

• G06F11/3089 Primary

  Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents (software debugging using additional hardware using a specific debug interface G06F11/3656; performance evaluation by tracing or monitoring G06F11/3466) · CPC title