Data processing apparatus and method of processing data

Patent metadata

Field	Value
Publication number	US-9537505-B2
Application number	US-201514847281-A
Country	US
Kind code	B2
Filing date	Sep 8, 2015
Priority date	Sep 8, 2014
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A data processing apparatus includes an inputting portion; a first retrieving portion; a second retrieving portion; a clock determining portion; a first serial parallel converting portion; a second serial parallel converting portion; and a combining portion. The inputting portion receives a serial data including a clock bit. The first retrieving portion obtains a first retrieved data. The second retrieving portion obtains a second retrieved data. The clock determining portion determines whether the clock bit is included in the first retrieved data or the second retrieved data. The first serial parallel converting portion performs parallel conversion to obtain a first parallel data. The second serial parallel converting portion performs parallel conversion to obtain a second parallel data. The combining portion combines the first parallel data and the second parallel data to output a parallel data.

First claim

What is claimed is:

1. A data processing apparatus, comprising:
an inputting circuit that receives a serial data formed of a sequence of serial data blocks of N bits (N is a natural number greater than 2) and including a clock bit;
a first retrieving circuit that retrieves and obtains a data of K bits (K is a natural number greater than N, K>N) from each of the serial data blocks as a first retrieved data;
a second retrieving circuit that retrieves and obtains a data of L bits (L is a difference between N and K, L=K−N) from each of the serial data blocks as a second retrieved data;
a clock determining circuit that determines whether the clock bit is included in one of the first retrieved data and the second retrieved data;
a first serial parallel converting circuit that performs parallel conversion to one of the first retrieved data and the second retrieved data that includes the clock bit according to a determination result of the clock determining portion so that the first serial parallel converting circuit obtains a first parallel data;
a second serial parallel converting circuit that performs parallel conversion to the other one of the first retrieved data and the second retrieved data that does not include the clock bit according to the determination result of the clock determining portion so that the second serial parallel converting circuit obtains a second parallel data; and
a combining circuit that combines the first parallel data and the second parallel data to output a parallel data of N bits.

2. The data processing apparatus according to claim 1 , further comprising a clock signal generating circuit that generates a first clock signal and a second clock signal having a phase different from that of the first clock signal according to the serial data,
wherein said first retrieving circuit retrieves the data of K bits from each of the serial data blocks according to the first clock signal, and
said second retrieving circuit retrieves the data of L bits from each of the serial data blocks according to the second clock signal.

3. The data processing apparatus according to claim 1 , wherein said first retrieving circuit and said second retrieving circuit alternately retrieve the data per one bit from each of the serial data blocks.

4. The data processing apparatus according to claim 1 , further comprising a first latching circuit that latches the data of K bits from each of the serial data blocks, and supplies a first latch data to the clock determining portion; and
a second latching circuit that latches the data of L bits from each of the serial data blocks, and supplies a second latch data to the clock determining portion,
wherein said clock determining circuit determines whether the clock bit is included in the one of the first retrieved data and the second retrieved data according to the first latch data and the second latch data.

5. The data processing apparatus according to claim 1 , wherein said combining circuit removes the clock bit from the first parallel data to obtain the first parallel data without the clock bit, and
said combining circuit combines the first parallel data without the clock bit and the second parallel data to output the parallel data of N bits.

6. A method of processing data, comprising:
an input receiving step, in which a serial data formed of a sequence of serial data blocks of N bits (N is a natural number greater than 2) and including a clock bit is received;
a first retrieving step, in which a data of K bits (K is a natural number greater than N, K>N) is retrieved and obtained from each of the serial data blocks as a first retrieved data;
a second retrieving step, in which a data of L bits (L is a difference between N and K, L=K−N) is retrieved and obtained from each of the serial data blocks as a second retrieved data;
a clock determining step, in which it is determined whether the clock bit is included in one of the first retrieved data and the second retrieved data;
a first serial parallel converting step, in which parallel conversion is performed to one of the first retrieved data and the second retrieved data that includes the clock bit according to a determination result of the clock determining step so that a first parallel data is obtained;
a second serial parallel converting step, in which parallel conversion is performed to the other one of the first retrieved data and the second retrieved data that does not include the clock bit according to the determination result of the clock determining step so that a second parallel data is obtained; and
a combining step, in which the first parallel data and the second parallel data are combined, and a parallel data of N bits is output.

7. The method of processing data according to claim 6 , further comprising a clock signal generating step, in which a first clock signal and a second clock signal having a phase different from that of the first clock signal are generated according to the serial data,
wherein, in the first retrieving step, said data of K bits is retrieved from each of the serial data blocks according to the first clock signal, and
in the second retrieving step, said data of L bits is retrieved from each of the serial data blocks according to the second clock signal.

8. The method of processing data according to claim 6 , wherein said first retrieving step and said second retrieving step are conducted alternately to retrieve the data per one bit from each of the serial data blocks.

9. The method of processing data according to claim 6 , further comprising a first latching step of latching the data of K bits from each of the serial data blocks, and of supplying a first latch data to the clock determining step; and
a second latching step of latching the data of L bits from each of the serial data blocks, and of supplying a second latch data to the clock determining step,
wherein in the clock determining step, it is to determine whether the clock bit is included in the one of the first retrieved data and the second retrieved data according to the first latch data and the second latch data.

10. The method of processing data according to claim 6 , wherein in the combining step, said clock bit is removed from the first parallel data to obtain the first parallel data without the clock bit, and
said first parallel data without the clock bit and said second parallel data are combined to output the parallel data of N bits.

11. A data processing apparatus, comprising:
an inputting circuit that receives a serial data formed of a sequence of serial data blocks of a plurality of bits and including a clock bit;
a plurality of retrieving circuits that retrieve and obtain a data from each of the serial data blocks as a plurality of retrieved data;
a clock determining circuit that determines whether the clock bit is included in one of the retrieved data;
a first serial parallel converting circuit that performs parallel conversion to one of the retrieved data that includes the clock bit according to a determination result of the clock determining circuit so that the first serial parallel converting circuit obtains a first parallel data;
a plurality of second serial parallel converting circuits that perform parallel conversion to the other ones of the retrieved data that do not include the clock bit according to the determination result of the clock determining circuit so that the second serial parallel converting circuits obtain a plurality of second parallel data; and
a combining circuit that combines the first parallel data and the second parallel data to output a parallel data.

12. The data processing apparatus according to claim 11 , further comprising a

Assignees

• Lapis Semiconductor Co Ltd

Inventors

• Ichikura Hiroyoshi
• Harayama Kunihiro
• Hasegawa Hideaki

Classifications

• H03M9/00 Primary

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H04L7/044

  using a single bit, e.g. start stop bit · CPC title

• H04L7/0337

  Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals · CPC title

• H04L7/0004

  Initialisation of the receiver (H04L7/0075 and H04L7/10 take precedence) · CPC title