Bit-flipping LDPC decoding algorithm with hard channel information

Patent metadata

Field	Value
Publication number	US-10148287-B2
Application number	US-201615346158-A
Country	US
Kind code	B2
Filing date	Nov 8, 2016
Priority date	Nov 8, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

Memory systems may include a memory storage, and an error correcting code (ECC) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.

First claim

What is claimed is:

1. A memory system, comprising:
a memory storage; and
an error correcting code (ECC) unit suitable for:
determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process;
updating a flipping indicator of a variable node, wherein the flipping indicator is based on at least two conditions including hard channel information of the variable node;
comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process;
flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold;
updating the flipping threshold associated with the decoding process iteratively based on at least two conditions including an iteration number of the decoding process and a condition of a previous decoding iteration; and
ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.

2. The memory system of claim 1 , wherein another condition on which updating the flipping indicator of the variable node is based includes a number of unsatisfied check nodes adjacent to the variable node.

3. The memory system of claim 1 , wherein the ECC unit is further suitable for updating the flipping indicator of the variable node by setting the flipping indicator of the variable node to the determined number of unsatisfied check nodes in the decoding iteration when the hard channel information of the variable node is equal to the channel output of the decoding iteration of the variable node.

4. The memory system of claim 1 , wherein the condition of the previous decoding iteration includes a number of unsatisfied check nodes of the previous decoding iteration, or a number of variable nodes flipped in the previous decoding iteration.

5. The memory system of claim 1 , wherein the ECC unit is further suitable for determining the decoding process is successful when a determined number of unsatisfied checks is zero.

6. A method, comprising:
determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process;
updating a flipping indicator of a variable node, wherein the flipping indicator is based on at least two conditions including hard channel information of the variable node and a condition of a previous decoding iteration;
comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process;
flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold;
updating the flipping threshold associated with the decoding process iteratively based on at least two conditions including an iteration number of the decoding process; and
ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.

7. The method of claim 6 , wherein another condition on which updating the flipping indicator of the variable node is based includes a number of unsatisfied check nodes adjacent to the variable node.

8. The method of claim 6 , further comprising updating the flipping indicator of the variable node by setting the flipping indicator of the variable node to the determined number of unsatisfied check nodes in the decoding iteration when the hard channel information of the variable node is equal to the channel output of the decoding iteration of the variable node.

9. The method of claim 6 , wherein the condition of the previous decoding iteration includes a number of unsatisfied check nodes of the previous decoding iteration, or a number of variable nodes flipped in the previous decoding iteration.

10. The method of claim 6 , further comprising determining the decoding process is successful when a determined number of unsatisfied checks is zero.

11. A memory device, comprising:
a memory storage; and
an error correcting code (ECC) unit configured to:
determine a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process;
update a flipping indicator of a variable node, wherein the flipping indicator is based on at least two conditions including hard channel information of the variable node;
compare the flipping indicator of the variable node with a flipping threshold associated with the decoding process;
flip a bit of the variable node when the flipping indicator is greater than the flipping threshold;
updating the flipping threshold associated with the decoding process iteratively based on at least two conditions including an iteration number of the decoding process and a condition of a previous decoding iteration; and
end the decoding process when decoding is determined to be successful or a maximal iteration number is reached.

12. The memory device of claim 11 , wherein another condition on which updating the flipping indicator of the variable node is based includes a number of unsatisfied check nodes adjacent to the variable node.

13. The memory device of claim 11 , wherein the ECC unit is further configured to update the flipping indicator of the variable node by setting the flipping indicator of the variable node to the determined number of unsatisfied check nodes in the decoding iteration when the hard channel information of the variable node is equal to the channel output of the decoding iteration of the variable node.

14. The memory device of claim 10 , wherein the condition of the previous decoding iteration includes a number of unsatisfied check nodes of the previous decoding iteration, or a number of variable nodes flipped in the previous decoding iteration.

15. The memory device of claim 11 , wherein the ECC unit is further configured to determine the decoding process is successful when a determined number of unsatisfied checks is zero.

Assignees

• Sk Hynix Inc

Inventors

• Xiong Chenrong
• Zhang Fan
• Bhatia Aman
• Prabhakar Abhiram
• Chou Hongchich
• Kumar Naveen

Classifications

• H03M13/1108 Primary

  Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F3/064

  Management of blocks · CPC title

• H03M13/1128

  Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title