Systems and methods for bit flipping decoding with reliability inputs

US9385753B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9385753-B2
Application numberUS-201414172420-A
CountryUS
Kind codeB2
Filing dateFeb 4, 2014
Priority dateFeb 14, 2013
Publication dateJul 5, 2016
Grant dateJul 5, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Systems and methods are provided for decoding data. A decoder receives a variable node value and reliability data for a variable node, and check node values for check nodes associated with the variable node. Circuitry generates an updated variable node value, based on the received reliability data and the received check node values. The circuitry also generates, for at least one check node, an updated check node value based on the updated variable node value.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for decoding data, comprising: receiving a variable node value and reliability data for a variable node, and check node values for check nodes associated with the variable node, wherein the check nodes include a number of check nodes that have a first check node value; selecting, from a lookup table listing a plurality of functions, a function that takes as inputs the reliability data and the number of check nodes; generating, by a circuitry, an updated variable node value, by executing the selected function, wherein the selected function comprises determining whether the number of check nodes exceeds a predetermined threshold; and generating, by the circuitry and for at least one check node, an updated check node value based on the updated variable node value. 2. The method of claim 1 , further comprising determining whether updated check node values for the at least one check node satisfy a decoding convergence condition. 3. The method of claim 1 , wherein the lookup table is a first lookup table, and wherein the selecting from the first lookup table comprises: determining a respective number of check nodes that have each of a plurality of check node values to generate a tuple; retrieving an index corresponding to the tuple from a second lookup table; and selecting the function from the first lookup table based on the index. 4. The method of claim 1 , further comprising: in response to determining that the updated variable node value is different from a previous value of the variable node value, storing the updated variable node value in memory. 5. The method of claim 1 , wherein generating the updated check node value for at least one check node is in response to determining that the updated variable node value is different from a previous value of the variable node value. 6. The method of claim 1 , wherein the selected function is a first function, and further comprising generating, by the circuitry, updated reliability data for the variable node, according to a second function based on the received reliability data and received check node values. 7. The method of claim 6 , wherein the second function is based on the number of check nodes having the first check node value. 8. The method of claim 1 , wherein the selected function is a first function, and further comprising: receiving check reliability data for the check nodes associated with the variable node, wherein the first function is further based on the received check reliability data; and processing, by the circuitry and for at least one check node, check reliability data for the check node, according to a second function based on the received reliability data, the received check node values, and the received check reliability data. 9. The method of claim 1 , wherein the check nodes in the number of check nodes are unsatisfied check nodes or neighboring check nodes. 10. The method of claim 1 , further comprising selecting the predetermined threshold based on the reliability data. 11. A decoder comprising decoding circuitry communicatively coupled to a memory, wherein the decoding circuitry is configured to: receive a variable node value and reliability data for a variable node, and check node values for check nodes associated with the variable node, wherein the check nodes include a number of check nodes that have a first check node value; select, from a lookup table listing a plurality of functions, a function that takes as inputs the reliability data and the number of check nodes; generate an updated variable node value, by executing the selected function, wherein the selected function comprises determining whether the number of check nodes exceeds a predetermined threshold; and generate, for at least one check node, an updated check node value based on the updated variable node value. 12. The decoder of claim 11 , wherein the decoding circuitry is further configured to determine whether updated check node values for the at least one check node satisfy a decoding convergence condition. 13. The decoder of claim 11 , wherein the lookup table is a first lookup table, and wherein the decoding circuitry configured to select from the first lookup table is further configured to: determine a respective number of check nodes that have each of a plurality of check node values to generate a tuple; retrieve an index corresponding to the tuple from a second lookup table; and select the function from the first lookup table based on the index. 14. The decoder of claim 11 , wherein the decoding circuitry is further configured to store the updated variable node in memory in response to determining that the updated variable node value is different from a previous value of the variable node value, storing the updated variable node value in memory. 15. The decoder of claim 11 , wherein the decoding circuitry generates the updated check node value for at least one check node in response to determining that the updated variable node value is different from a previous value of the variable node value. 16. The decoder of claim 11 , wherein the selected function is a first function, and wherein the decoding circuitry is further configured to generate updated reliability data for the variable node, according to a second function based on the received reliability data and received check node values. 17. The decoder of claim 16 , wherein the second function is based on the number of check nodes having the first check node value. 18. The decoder of claim 11 , wherein the selected function is a first function, and wherein the decoding circuitry is further configured to: receive check reliability data for the check nodes associated with the variable node, wherein the first function is further based on the received check reliability data; and process, for at least one check node, check reliability data for the check node, according to a second function based on the received reliability data, the received check node values, and the received check reliability data. 19. The decoder of claim 11 , wherein the check nodes in the number of check nodes are unsatisfied check nodes or neighboring check nodes. 20. The decoder of claim 11 , wherein the decoder is further configured to select the predetermined threshold based on the reliability data.

Assignees

Inventors

Classifications

  • Parity-check or generator matrices with non-binary elements, e.g. for non-binary LDPC codes · CPC title

  • Hard decision decoding, e.g. bit flipping, modified or weighted bit flipping · CPC title

  • Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel · CPC title

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What does patent US9385753B2 cover?
Systems and methods are provided for decoding data. A decoder receives a variable node value and reliability data for a variable node, and check node values for check nodes associated with the variable node. Circuitry generates an updated variable node value, based on the received reliability data and the received check node values. The circuitry also generates, for at least one check node, an …
Who is the assignee on this patent?
Marvell World Trade Ltd
What technology area does this patent fall under?
Primary CPC classification H03M13/1108. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 05 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).