Multi-chip package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10147706-B2
Application number	US-201715623891-A
Country	US
Kind code	B2
Filing date	Jun 15, 2017
Priority date	Oct 24, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

A multi-chip package includes a package substrate including a first substrate pad, a first group of semiconductor chips stacked on the package substrate, each of the first group of the semiconductor chips including bonding pads, first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group, a first conductive wire downwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad, and a second conductive wire upwardly extended from the bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps.

First claim

What is claimed is:

1. A multi-chip package, comprising:
a package substrate including a first substrate pad;
a first group of semiconductor chips stacked on the package substrate, each one of the semiconductor chips in the first group including at least one bonding pad;
first stud bumps arranged on the bonding pads of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group;
a first conductive wire downwardly extended from the at least one bonding pad of the lowermost semiconductor chip in the first group and connected to the first substrate pad; and
a second conductive wire upwardly extended from the at least one bonding pad of the lowermost semiconductor chip in the first group and sequentially connected to the first stud bumps, the second conductive wire being a single wire continuously extending from the lowermost semiconductor chip to the first stud bumps in a steplike shape.

2. The multi-chip package as claimed in claim 1 , wherein the semiconductor chips in the first group are stacked in a steplike shape to expose the bonding pads.

3. The multi-chip package as claimed in claim 1 , wherein the semiconductor chips in the first group have substantially a same size.

4. The multi-chip package as claimed in claim 1 , wherein the first conductive wire includes a first ball attached to the at least one bonding pad of the lowermost semiconductor chip in the first group of the semiconductor chips.

5. The multi-chip package as claimed in claim 4 , wherein the second conductive wire includes a second ball attached to the first ball.

6. The multi-chip package as claimed in claim 5 , wherein the second wire is continuously connected between the second ball and the first stud bump, and between the first stud bumps.

7. The multi-chip package as claimed in claim 1 , wherein the package substrate further includes a second substrate pad.

8. The multi-chip package as claimed in claim 7 , further comprising:
a second group of semiconductor chips stacked on an uppermost semiconductor chip of the first group of the semiconductor chips, each one of the semiconductor chips in the second group including at least one bonding pad;
second stud bumps arranged on the bonding pads of the second group of the semiconductor chips except for a lowermost semiconductor chip in the second group;
a third conductive wire downwardly extended from the at least one bonding pad of the lowermost semiconductor chip in the second group and connected to the second substrate pad; and
a fourth conductive wire upwardly extended from the at least one bonding pad of the lowermost semiconductor chip in the second group and sequentially connected to the second stud bumps.

9. The multi-chip package as claimed in claim 8 , wherein the semiconductor chips in the second group are stacked in a steplike shape along a direction opposite to a stacking direction of the first group of the semiconductor chips to expose the bonding pads of the second group of the semiconductor chips.

10. The multi-chip package as claimed in claim 8 , wherein the semiconductor chips in the second group have substantially a same size.

11. The multi-chip package as claimed in claim 10 , wherein a number of semiconductor chips in the second group of the semiconductor chips is substantially the same as that of the semiconductor chips in the first group of the semiconductor chips.

12. The multi-chip package as claimed in claim 8 , wherein the third conductive wire includes a third ball attached to the at least one bonding pad of the lowermost semiconductor chip in the second group.

13. The multi-chip package as claimed in claim 12 , wherein the fourth conductive wire includes a fourth ball attached to the third ball.

14. The multi-chip package as claimed in claim 13 , wherein the fourth conductive wire includes a single wire continuously connected between the fourth ball and the second stud bump, and between the second stud bumps.

15. A multi-chip package, comprising:
a package substrate including a substrate pad;
first to fourth semiconductor chips stacked on the package substrate in a steplike shape, each of the first to fourth semiconductor chips including at least one bonding pad, and the first to fourth semiconductor chips having substantially the same size;
stud bumps arranged on the bonding pads of the second to fourth semiconductor chips;
a first conductive wire including a first ball attached to the at least one bonding pad of the first semiconductor chip, the first conductive wire downwardly extended from the first ball and connected to the substrate pad; and
a second conductive wire including a second ball attached to the first ball, the second conductive wire upwardly extended from the second ball and sequentially connected to the stud bumps.

16. The multi-chip package as claimed in claim 15 , wherein the second wire includes a single wire continuously connected between the second ball and the stud bump, and between the stud bumps.

17. A multi-chip package, comprising:
a package substrate including a first substrate pad;
a first group of semiconductor chips stacked on the package substrate, each one of the semiconductor chips in the first group including at least one bonding pad;
a first stud bump on each bonding pad of the first group of the semiconductor chips except for a lowermost semiconductor chip in the first group;
a first conductive wire extending from the at least one bonding pad of the lowermost semiconductor chip in the first group to contact the first substrate pad; and
a second conductive wire extending continuously from the at least one bonding pad of the lowermost semiconductor chip in the first group to contact at least one first stud bump on each of the semiconductor chips in the first group, the second conductive wire being a single wire continuously extending from the lowermost semiconductor chip to the first stud bumps in a steplike shape.

18. The multi-chip package as claimed in claim 17 , wherein the semiconductor chips in the first group are stacked in a steplike structure, the second conductive wire extending continuously and sequentially along each step of the steplike structure above the lowermost semiconductor chip.

19. The multi-chip package as claimed in claim 17 , wherein the first and second conductive wires are connected to each other on the lowermost semiconductor chip via a ball.

20. The multi-chip package as claimed in claim 17 , wherein each of the first and the second conductive wires includes two linear wire portions between every two semiconductor chips, the two linear wire portions being connected to each other at a non-zero angle.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Won-Gil
• Kim Byong-Joo
• Lee Yong-Je
• Lee Jae-Heung
• Ha Seung-Weon

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/751

  of bond wires · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title