Multi-chip package and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9252123-B2
Application number	US-201414505802-A
Country	US
Kind code	B2
Filing date	Oct 3, 2014
Priority date	Oct 18, 2011
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes.

First claim

What is claimed is:

1. A method of manufacturing a multi-chip package, the method comprising:
providing a package substrate including a plurality of substrate pads disposed on an upper surface of the package substrate, the substrate pads including at least a ground pad and at least a signal pad;
stacking a first semiconductor chip on the package substrate, the first semiconductor chip including at least a first bonding pad disposed on an upper surface of the first semiconductor chip;
stacking at least a second semiconductor chip on the first semiconductor chip such that the first bonding pad remains exposed, the second semiconductor chip including at least a second bonding pad disposed on an upper surface of the second semiconductor chip;
forming a first stud bump on an upper surface of the first bonding pad;
forming a first conductive wire to extend from a first ground pad of the plurality of substrate pads to an upper surface of the first stud bump;
forming a first nail head bonding bump on the first stud bump and first conductive wire; and
after the first semiconductor chip has been electrically connected to the first ground pad:
forming a second stud bump on an upper surface of the second bonding pad;
forming a second conductive wire extending from an upper surface of the first nail head bonding bump to the second stud bump; and
testing an electrical connectivity of the first semiconductor chip, wherein the step of testing is perform after forming the first conductive wire and before forming the second stud bump.

2. The method of claim 1 , further comprising:
after forming the second conductive wire, forming a second nail head bonding bump on the second stud bump and second conductive wire.

3. The method of claim 1 , wherein the first stud bump, first conductive wire, and first nail head are formed from a same metal line.

4. The method of claim 1 , wherein a surface area of the first stud bump in contact with the first bonding pad is at least 50% the size of the surface area of the upper surface of the first bonding pad.

5. The method of claim 4 , wherein a surface area of a lower surface of the first nail head bonding bump that faces the upper surface of the first stud bump is at least 50% of the size of the surface area of the upper surface of the first stud bump.

6. A method of manufacturing a multi-chip package, comprising:
providing a package substrate including a plurality of substrate pads disposed on an upper surface of the package substrate, the substrate pads including at least a ground pad and at least a signal pad;
stacking a first semiconductor chip on the package substrate, the first semiconductor chip including at least a first bonding pad disposed on an upper surface of the first semiconductor chip;
stacking at least a second semiconductor chip on the first semiconductor chip such that the first bonding pad remains exposed, the second semiconductor chip including at least a second bonding pad disposed on an upper surface of the second semiconductor chip;
forming a first electrical connection between the first semiconductor chip and a ground pad on the package substrate, an end of the electrical connection being formed on a first conductive bump of the first semiconductor chip; and
after electrically connecting the first semiconductor chip to the ground pad, forming a second electrical connection from the first semiconductor chip to the second semiconductor chip,
wherein the step of forming a second electrical connection from the first semiconductor chip to the second semiconductor chip comprises the steps of:
forming a second conductive bump on the end of the first electrical connection disposed on the first conductive bump of the first semiconductor chip;
forming a first conductive bump on the second semiconductor chip; and
forming a first conductive wire extending from the second conductive bump of the first semiconductor chip to the first conductive bump on the second semiconductor chip; and
testing an electrical connectivity of the first semiconductor chip, wherein the step of testing is performed after forming the first electrical connection and before forming the first conductive bump on the second semiconductor chip.

7. The method of claim 6 , wherein:
forming the first conductive bump on the first semiconductor chip comprises forming a first stud bump on an upper surface of the first bonding pad;
forming the second conductive bump on an end of the of the first electrical connection comprises forming a first nail head bonding bump on the first stud bump and first electrical connection;
forming a first conductive bump on the second semiconductor chip comprises forming a second stud bump on an upper surface of the second bonding pad.

8. The method of claim 6 , further comprising:
stacking a third semiconductor chip on the second semiconductor chip such that the second bonding pad remains exposed, the third semiconductor chip including at least a third bonding pad disposed on an upper surface of the third semiconductor chip;
electrically connecting the third semiconductor chip and the second semiconductor chip,
wherein the step of stacking the third semiconductor chip is performed before the step of electrically connecting the first semiconductor chip and the second semiconductor chip, and
wherein the step of electrically connecting the third semiconductor chip and the second semiconductor chip is performed after the step of electrically connecting the first semiconductor chip and the second semiconductor chip.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Won-Gil
• Park Se-Yeoul
• Jin Ho-Tae
• Kim Byong-Joo
• Lee Yong-Je
• Park Han-Ki

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title