Apparatus, system and method for offloading collision check operations in a storage device

Patent metadata

Field	Value
Publication number	US-10146440-B2
Application number	US-201615385791-A
Country	US
Kind code	B2
Filing date	Dec 20, 2016
Priority date	Dec 20, 2016
Publication date	Dec 4, 2018
Grant date	Dec 4, 2018

Abstract

Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.

First claim

What is claimed:

1. An apparatus, comprising:
a non-volatile memory;
a collision check unit including a collision table including logical addresses for pending Input/Output (I/O) requests;
a transfer buffer to buffer data being written and read from the non-volatile memory; and
a memory controller to:
receive an I/O request to a target logical address in the non-volatile memory, wherein the I/O request comprises at least one of a read and write request to the target logical address;
send the logical address to the collision check unit;
allocate resources to transfer data with respect to the transfer buffer for the I/O request while the collision check unit determines whether the collision table includes the target logical address; and
wherein the collision check unit determines whether the collision table includes the target logical address and returns an indication of whether the collision table includes the target logical address to indicate that current data for the target logical address is already in the transfer buffer.

2. The apparatus of claim 1 , wherein the memory controller is further to:
free the allocated resources in response to determine the collision table includes the target logical address.

3. The apparatus of claim 1 , wherein in response to determine that the collision table does not include the target logical address, the memory controller is further to:
select a free index entry in the collision table;
indicate the target logical address in the selected free index entry; and
indicate the selected free index entry as not free.

4. The apparatus of claim 1 , wherein the collision check unit is comprised of multiple collision check sub-units, wherein each of the collision check sub-units stores a subset of entries in the collision table and performs a parallel search on the subset of entries in the collision table to determine whether the target logical address matches one of the subset of entries searched by the collision check sub-unit.

5. The apparatus of claim 1 , wherein the memory controller is further to:
write data for the I/O request, comprising a write request, to the transfer buffer at a location in the transfer buffer already having data for the target logical address when the collision check unit returns the indication that the collision table already includes the target logical address; and
read data for the I/O request, comprising a read request, at an address in the transfer buffer already including the data for the target logical address when the collision check unit returns the indication that the collision table already includes the target logical address.

6. The apparatus of claim 1 , wherein the memory controller is further to:
receive a defragmentation request to move data at a source logical address in the non-volatile memory to a destination logical address in the non-volatile memory;
in response to the defragmentation request:
send the source logical address to the collision check unit to determine whether the collision table includes the source logical address;
allocate resources to transfer data for the source logical address from the non-volatile memory to the transfer buffer while the collision check unit is determining whether the collision table includes the source logical address;
use the allocated resources to transfer data for the source logical address to the transfer buffer in response to determining that the collision table includes the source logical address; and
issue a command to the collision check unit to indicate the destination logical address in the collision table in response to determining that the collision table does not include the source logical address, wherein the collision check unit indicates the destination logical address in the collision table.

7. The apparatus of claim 6 , wherein the memory controller is further to:
fail the defragmentation request in response to determining that the collision table includes the source logical address.

8. The apparatus of claim 1 , wherein the collision table includes index entries, each index entry having a free flag indicating whether the index entry is free and available for use and a search flag indicating whether the collision check unit will determine whether the index entry includes the target logical address,
wherein the collision check unit is further to ignore one of the index entries when determining whether one of the index entries includes the target logical address when the search flag for the index entry indicates to not search or when the free flag indicates that the index entry is free.

9. The apparatus of claim 8 , wherein in response to determining that the collision table does not include the index entry, the collision check unit is further to:
select an index entry in the collision table having a free flag indicating that the index entry is free;
indicate the target logical address in the selected index entry; and
set the free flag in the selected index entry to indicate not free.

10. The apparatus of claim 9 , wherein the memory controller is further to:
indicate in the search flag for the selected index entry to not determine whether the index entry includes the target logical address when the I/O request comprises a read access; and
indicate in the search flag for the selected index entry to determine whether the index entry includes the target logical address when the I/O request comprises a write access.

11. The apparatus of claim 1 , wherein the collision check unit and the transfer buffer are implemented in the memory controller.

12. A system, comprising:
a host computer; and
a non-volatile memory storage device coupled to the host computer, wherein the host computer communicates Input/Output (I/O) requests to the non-volatile memory storage device, comprising:
a non-volatile memory;
a collision check unit including a collision table including logical addresses for pending I/O requests;
a transfer buffer to buffer data being written and read from the non-volatile memory; and
a memory controller to:
receive an I/O request to a target logical address in the non-volatile memory, wherein the I/O request comprises at least one of a read and write request to the target logical address;
send the logical address to the collision check unit;
allocate resources to transfer data with respect to the transfer buffer for the I/O request while the collision check unit determines whether the collision table includes the target logical address; and
wherein the collision check unit determines whether the collision table includes the target logical address and returns an indication of whether the collision table includes the target logical address to indicate that current data for the target logical address is already in the transfer buffer.

13. The system of claim 12 , wherein in response to determine that the collision table does not include the target logical address, the memory controller is further to:
select a free index entry in the collision table;
indicate the target logical address in the selected free index entry; and
indicate the selected free index entry as not free.

14. The system of claim 12 , wherein the memory controller is further to:
write data for the I/O request, comprising a write request, to the transfer buffer at a location in the transfer buffer already having data for the target logical address when the collision check unit returns the indication that the collision table already includes the target logical address; and
read data for the I/O request, comprising a read request, at an address in the transfer buffer already includi

Assignees

• Intel Corp

Inventors

• Li Peng
• Ramalingam Anand S
• Khan Jawad B
• Lui William K
• Narayanan Divya
• Trika Sanjeev N

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title