Techniques for identifying read/write access collisions for a storage medium

Patent metadata

Field	Value
Publication number	US-9323664-B2
Application number	US-201313948702-A
Country	US
Kind code	B2
Filing date	Jul 23, 2013
Priority date	Jul 23, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

Examples are disclosed for identifying read/write access collisions for a storage medium. In some examples, a plurality of write access requests for access to a storage medium may be received at a controller for a storage medium. The plurality of write access requests may be associated with separate logical block address (LBA) ranges. The separate write LBA ranges may be stored to sets of first registers. A read access request to the storage medium may also be received and a read LBA range associated with the read access request may be stored to a set of second registers. The separate stored write LBA ranges may then be compared to the read LBA range to identify overlapping ranges that may indicate read/write access collisions to the storage medium. Other examples are described and claimed.

First claim

What is claimed is:

1. An apparatus comprising:
a processor circuit to control access to a storage medium;
a write access module for execution by the processor circuit to receive a plurality of write access requests to the storage medium, each write access request associated with a separate logical block address (LBA) range, the write access module to store a write LBA range for each write access request in sets of registers included in first registers;
a read access module for execution by the processor circuit to receive a read access request to the storage medium associated with a read LBA range, the read access module to store the read LBA range to a set of registers in second registers;
a compare module for execution by the processor circuit to compare the stored read LBA range to each of the stored write LBA ranges to determine whether the stored read LBA range overlaps with any one of the stored write LBA ranges;
an assign module for execution by the processor circuit to assign a separate index value to each stored write LBA range, the separate index value to indicate a relative time of a given stored write LBA range for a given write access request compared to other stored write LBA ranges for other write access requests from among the plurality of write access requests; and
a priority module for execution by the processor circuit to compare index values for first and second stored write LBA ranges based on the first and second stored write LBA ranges overlapping with the stored read LBA range, the priority module to indicate which of the first and the second stored write LBA ranges has a most recent write access request that has an overlapping stored write LBA range with the stored read LBA range based on the comparison of the index values.

2. The apparatus of claim 1 , comprising:
the assign module to assign the separate index value to each stored write LBA range such that a higher index value is associated with the more recent write access request; and
the priority module to indicate which of the first and the second stored write LBA ranges has a higher index value after the comparison of the index values to indicate the most recent write access request having the overlapping stored write LBA range with the stored read LBA range.

3. The apparatus of claim 1 , comprising:
the priority module to store an indication to third registers to indicate the most recent write access request having the overlapping stored write LBA range with the stored read LBA range.

4. The apparatus of claim 3 , comprising the indication to include the index value assigned to the overlapping stored write LBA range.

5. The apparatus of claim 1 , the write access module to store the write LBA range for each write access request comprises the write access module to store a start write LBA in a first portion of registers for a respective set of registers from among the first registers and an end write LBA in a second portion of registers for the respective set of registers.

6. The apparatus of claim 5 , the read access module to store the read LBA range for the read access request comprises the read access module to store a start read LBA in a first portion of registers for the set of second registers and an end read LBA in a second portion of registers for the set of second registers.

7. The apparatus of claim 1 , the compare module to compare the stored read LBA range to each of the stored write LBA ranges comprises the compare module to compare all the stored write LBA ranges to the stored read LBA range in a single clock cycle of the processor circuit.

8. The apparatus of claim 1 , the compare module to compare the stored read LBA range to each of the stored write LBA ranges comprises the compare module to compare a first group of stored write LBA ranges to the stored read LBA range in a first clock cycle of the processor circuit and compare a second group of stored write LBA ranges to the stored read LBA range in a second, subsequent clock cycle.

9. The apparatus of claim 1 , comprising:
the write access module to receive an indication that a given write access request has a stored write LBA range in a respective set of the first registers that has been completed before the read access request has been received; and
a mask module to mask a determination of whether the read LBA range overlaps with the stored write LBA range such that the read LBA range is determined by the compare module to not overlap the stored write LBA range for the given write access request that has been completed.

10. The apparatus of claim 1 , comprising the storage medium including a solid state drive (SSD) that has non-volatile memory that includes at least one of 3-dimensional cross-point memory, flash memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory, nanowire, ferroelectric transistor random access memory (FeTRAM or FeRAM), nanowire or electrically erasable programmable read-only memory (EEPROM).

11. A method comprising:
receiving, at a processor circuit to control a storage medium, a plurality of write access requests to the storage medium, each write access request associated with a separate logical block address (LBA) write range;
storing a write LBA range for each write access request in sets of first registers;
receiving a read access request to the storage medium associated with a read LBA range;
storing the read LBA range to a set of second registers;
comparing the read LBA range stored to the set of second registers to each of the write LBA ranges stored to the first set of registers;
determining whether the read LBA range overlaps with any one of the write LBA ranges;
assigning a separate index value to each write LBA range, the separate index value to indicate a relative time of a given write LBA range for a given write access request compared to other write LBA ranges for other write access requests from among the plurality of write access requests;
comparing index values for first and second write LBA ranges based on the first and second write LBA ranges overlapping with the read LBA range; and
indicating which of the first and the second write LBA ranges has a most recent write access request having an overlapping write LBA range with the read LBA range based on comparing the index values.

12. The method of claim 11 , comprising:
assigning the separate index value to each write LBA range such that a higher index value is associated with the more recent write access request; and
indicating which of the first and the second write LBA ranges has a higher index value after comparing the index values to indicate the most recent write access request having the overlapping write LBA range with the read LBA range.

13. The method of claim 11 , comprising:
indicating the most recent write access request having the overlapping write LBA range with the read LBA range by storing the index value in third registers;
accessing the third register and delaying the read access request until after the most recent write access request having the overlapping write LBA range is completed.

14. The method of claim 11 , storing the write LBA range for each write access request comprises storing a start write LBA in a first portion of registers for a respective set of registers from among the first registers and an end write LBA in a second portion of registers for the respective set of registers.

15. The method of claim 11 , storing the read LBA range for the read access request comprises storing a start read LBA in a first portion of registers for the set of second registers and an end read LBA

Assignees

• Intel Corp

Inventors

• Yu Jason K
• Khan Jawad B
• Hartung Joerg
• Mangold Richard P

Classifications

• G06F3/0614 Primary

  Improving the reliability of storage systems · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F3/0671

  In-line storage system · CPC title