Virtual unifed instruction and data caches including storing program instructions and memory address in CAM indicated by store instruction containing bit directly indicating self modifying code

Patent metadata

Field	Value
Publication number	US-9747212-B2
Application number	US-201313835510-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

Execution of a store instruction to modify an instruction at a memory location identified by a memory address is requested. A cache controller stores the memory address and the modified data in an associative memory coupled to a data cache and an instruction cache. In addition, the modified data is stored in a second level cache without invalidating the memory location associated with the instruction cache.

First claim

What is claimed is:

1. A method for modifying program instructions comprising:
receiving a request to execute a store instruction to modify first data at a memory location identified by a memory address;
determining that one or more bits of the store instruction are set to directly indicate that second data referenced by the store instruction comprises a program instruction to replace the first data;
in response to determining that the one or more bits of the store instruction are set to directly indicate that the second data referenced by the store instruction comprises the program instruction, storing a first instruction cache memory address and the program instruction in an associative memory pipeline coupled between a data cache and an instruction cache, wherein a first level cache comprises the data cache, the instruction cache, and the associative memory pipeline;
receiving a fetch request specifying a second instruction cache memory address;
in response to receiving the fetch request, determining if the second instruction cache memory address matches the first instruction cache memory address; and
in response to determining that the second instruction cache memory address matches the first instruction cache memory address, protecting an instruction cache entry associated with the second instruction cache memory address from instruction fetches until the program instruction is written to the instruction cache.

2. The method of claim 1 , wherein protecting the instruction cache entry associated with the second instruction cache memory address from instruction fetches includes stalling an instruction pipeline.

3. The method of claim 1 , further comprising:
in response to the determining that the second instruction cache memory address matches the first instruction cache memory address, returning the program instruction for the second instruction cache memory address from the associative memory pipeline.

4. The method of claim 1 , wherein said storing the first instruction cache memory address and the program instruction in the associative memory pipeline coupled between the data cache and the instruction cache is performed without invalidating the instruction cache.

5. An apparatus comprising:
a first level cache comprising:
a data cache;
an instruction cache;
one or more cache controllers coupled to the data cache and the instruction cache;
and an associative memory coupled between the data cache and the instruction cache, the associative memory comprising a real address field and a modified line field;
wherein the one or more cache controllers are configured to:
receive a request to execute a store instruction to modify first data at a memory location identified by a memory address,
determine that one or more bits of the store instruction are set to directly indicate that second data referenced by the store instruction comprises a program instruction to replace the first data,
in response to determining that the one or more bits of the store instruction are set to directly indicate that the second data referenced by the store instruction comprises the program instruction, store a first instruction cache memory address and the program instruction in the associative memory,
receive a fetch request specifying a second instruction cache memory address,
in response to receipt of the fetch request, determine if the second instruction cache memory address matches the first instruction cache memory address, and
in response to a determination that the second instruction cache memory address matches the first instruction cache memory address, protect an instruction cache entry associated with the second instruction cache memory address from instruction fetches until the program instruction is written to the instruction cache; and

a second level cache coupled to the first level cache.

6. The apparatus of claim 5 , wherein the associative memory includes a content addressable memory.

7. The apparatus of claim 5 , wherein the associative memory includes a valid indicator field.

8. The apparatus of claim 5 , wherein the associative memory includes a ready indicator field.

9. The apparatus of claim 5 , further comprising a buffer coupled between the associative memory and the instruction cache.

10. The apparatus of claim 9 , wherein the buffer is a first-in first-out buffer.

11. The apparatus of claim 5 , wherein the one or more cache controllers are further configured to store the first instruction cache memory address and the program instruction in the associative memory without invalidating the instruction cache.

12. A computer program product for caching instructions, the computer program product comprising:
a non-transitory computer readable storage medium having computer usable program code embodied therewith, the computer usable program code comprising a computer usable program code configured to:
receive a request to execute a store instruction to modify first data at a memory location identified by a memory address;
determine that one or more bits of the store instruction are set to directly indicate that second data referenced by the store instruction comprises a program instruction to replace the first data;
in response to determining that the one or more bits of the store instruction are set to directly indicate that the second data referenced by the store instruction comprises the program instruction, store a first instruction cache memory address and the program instruction in an associative memory pipeline coupled between a data cache and an instruction cache, wherein a first level cache comprises the data cache, the instruction cache, and the associative memory pipeline;
receive a fetch request specifying a second instruction cache memory address,
in response to receipt of the fetch request, determine if the second instruction cache memory address matches the first instruction cache memory address, and
in response to a determination that the second instruction cache memory address matches the first instruction cache memory address, protect an instruction cache entry associated with the second instruction cache memory address from instruction fetches until the program instruction is written to the instruction cache.

13. The computer program product of claim 12 , wherein the computer usable program code configured to protect the instruction cache entry associated with the second instruction cache memory address from instruction fetches includes computer usable program code configured to stall an instruction pipeline.

14. The computer program product of claim 12 , wherein the computer usable program code is further configured to:
in response to the determination that the second instruction cache memory address matches the first instruction cache memory address, return the program instruction for the second instruction cache memory address from the associative memory pipeline.

15. The computer program product of claim 12 , wherein the computer usable program code configured to store the first instruction cache memory address and the program instruction in the associative memory pipeline is performed without invalidating the instruction cache.

Assignees

• IBM

Inventors

• Chen Jr Wen-Tzer Thomas
• Bell Jr Robert H
• Frey Bradly G

Classifications

• G06F12/0848 Primary

  Partitioned cache, e.g. separate instruction and operand caches · CPC title