Semiconductor device

Patent metadata

Field	Value
Publication number	US-10141368-B2
Application number	US-201615561992-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Mar 31, 2015
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

In a plane including the center line of a vertical through hole, it is assumed that a segment that connects a first point corresponding to the edge of an opening of an insulating layer and a second point corresponding to the edge of a second opening is a first segment, a segment that connects the second point and a third point corresponding to an intersection point between the second opening and a surface of the insulating layer is a second segment, and a segment that connects the third point and the first point is a third segment. In the insulating layer, the first area located on one side with respect to the first segment is larger than the sum of the second area surrounded by the first, the second and the third segments and the third area located on the other side with respect to the third segment.

First claim

The invention claimed is:

1. A semiconductor device comprising: a semiconductor substrate that has a first surface and a second surface opposite to each other and in which a through hole to extend from the first surface to the second surface is formed;
a first wiring that is provided on the first surface and has a portion located above a first opening of the through hole on the a first surface side;
an insulating layer that is provided on an inner surface of the through hole and the second surface and is continuous through a second opening of the through hole on the a second surface side; and
a second wiring that is provided on a surface of the insulating layer and is electrically connected to the first wiring in an opening of the insulating layer on the first surface side, wherein the through hole is a vertical hole, and on both sides of a center line of the through hole in a plane including the center line of the through hole, a segment that connects a first point corresponding to an edge of the opening of the insulating layer and a second point corresponding to an edge of the second opening is a first segment, a segment that connects the second point and a third point corresponding to an intersection point between the second opening and the surface of the insulating layer is a second segment, and a segment that connects the third point and the first point is a third segment, a first area of the insulating layer that is located on an inner surface side of the through hole with respect to the first segment is larger than the sum of a second area of the insulating layer that is surrounded by the first segment, the second segment, and the third segment and a third area of the insulating layer that is located on a side opposite the inner surface side of the through hole with respect to the third segment.

2. The semiconductor device according to claim 1 ,
wherein an inclination angle of the surface of the insulating layer at the first point is greater than an inclination angle of the surface of the insulating layer at the third point.

3. The semiconductor device according to claim 1 ,
wherein an average inclination angle of the surface of the insulating layer provided on the inner surface of the through hole is less than an average inclination angle of the inner surface of the through hole.

4. The semiconductor device according to claim 1 ,
wherein, when attention is paid to the regions on both sides of the center line of the through hole in the plane including the center line of the through hole, a distance between the first point and a fourth point corresponding to an edge of the first opening is greater than a width of the opening of the insulating layer.

5. The semiconductor device according to claim 1 ,
wherein the portion of the first wiring is a pad portion that covers the first opening, and
a distance between the edge of the first opening and the edge of the opening of the insulating layer is greater than a distance between the edge of the first opening and an edge of the pad portion.

6. The semiconductor device according to claim 1 ,
wherein an aspect ratio that is a value obtained by dividing a depth of the through hole by a width of the second opening is equal to or less than 1.

7. The semiconductor device according to claim 1 ,
wherein the insulating layer is made of a resin.

8. The semiconductor device according to claim 1 ,
wherein the surface of the insulating layer provided on the inner surface of the through hole is a continuous surface.

9. The semiconductor device according to claim 1 ,
wherein the surface of the insulating layer provided on the inner surface of the through hole and the surface of the insulating layer provided on the second surface are a continuous surface.

10. The semiconductor device according to claim 1 , further comprising:
a mounting substrate that has a third surface on which a plurality of third wirings are provided, and is provided so as to face the second surface,
wherein a plurality of avalanche photodiodes that operate in a Geiger mode are provided in the semiconductor substrate,
the through hole, the first wiring, and the second wiring are provided so as to correspond to each of the plurality of avalanche photodiodes,
each of the plurality of avalanche photodiodes is electrically connected to the corresponding second wiring through the corresponding first wiring, and
each of the plurality of third wirings is electrically connected to the corresponding second wiring through a bump electrode.

Assignees

• Hamamatsu Photonics Kk

Inventors

• Ishida Atsushi
• HOSOKAWA Noburo
• Nagano Terumasa
• Baba Takashi

Classifications

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10W20/2125

  Top-view shapes · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title