Semiconductor package structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-10141276-B2
Application number	US-201715599481-A
Country	US
Kind code	B2
Filing date	May 19, 2017
Priority date	Sep 9, 2016
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a redistribution structure, at least one package structure and a second encapsulant. The redistribution structure has a first surface and a second surface opposite to the first surface. The package structure is over the first surface and includes at least one die, a first encapsulant, a redistribution layer, and a plurality of second conductive terminals. The die has a plurality of first conductive terminals thereon. The first encapsulant encapsulates the die and exposes at least part of the first conductive terminals. The redistribution layer is over the first encapsulant and is electrically connected to the first conductive terminals. The second conductive terminals are electrically connected between the redistribution layer and the redistribution structure. The second encapsulant, encapsulates the package structure and exposes at least part of the second conductive terminals.

First claim

What is claimed is:

1. A semiconductor package structure, comprising:
a redistribution structure, having a first surface and a second surface opposite to the first surface;
at least one package structure over the first surface of the redistribution structure, wherein the at least one package structure comprises:
at least one die, having a plurality of first conductive terminals thereon;
a first encapsulant, encapsulating the at least one die, wherein the first encapsulant exposes at least part of the first conductive terminals;
a redistribution layer over the first encapsulant, wherein the redistribution layer is electrically connected to the first conductive terminals; and
a plurality of second conductive terminals, electrically connected between the redistribution layer and the redistribution structure; and

a second encapsulant, encapsulating the at least one package structure, wherein the second encapsulant exposes at least part of the second conductive terminals.

2. The semiconductor package structure according to claim 1 , wherein the redistribution structure comprises at least one dielectric layer and a plurality of conductive elements embedded in the dielectric layer, the conductive elements comprises:
a plurality of first bonding pads at the first surface of the redistribution structure, wherein the second conductive terminals are disposed corresponding to the first bonding pads;
a plurality of second bonding pads at the second surface of the redistribution structure; and
a plurality of interconnect structures, electrically connecting at least part of the first bonding pads with at least part of the second bonding pads.

3. The semiconductor package structure according to claim 1 , further comprising a plurality of solder balls over the second surface of the redistribution structure.

4. The semiconductor package structure according to claim 3 , wherein a first pitch between two adjacent first conductive terminals is smaller than a second pitch between two adjacent second conductive terminals, and the second pitch is smaller than a third pitch between two adjacent solder balls.

5. The semiconductor package structure according to claim 1 , wherein each of the second conductive terminals comprises a conductive pillar, a conductive bump, or a combination thereof.

6. The semiconductor package structure according to claim 1 , further comprising at least one passive device disposed on the first surface of the redistribution structure.

7. The semiconductor package structure according to claim 1 , further comprising at least one additional package structure on the first surface of the redistribution structure.

8. The semiconductor package structure according to claim 1 , wherein the redistribution structure includes a printed circuit board or an organic package substrate.

9. The semiconductor package structure according to claim 1 , further comprising at least one passive device disposed on the second surface of the redistribution structure.

Assignees

• Powertech Technology Inc

Inventors

• Hsu Hung-Hsin
• Lin Nan-Chun
• Chang Chien Shang-Yu

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title