Interconnect structures for wafer level package and methods of forming same

Patent metadata

Field	Value
Publication number	US-9373604-B2
Application number	US-201514686530-A
Country	US
Kind code	B2
Filing date	Apr 14, 2015
Priority date	Aug 20, 2014
Publication date	Jun 21, 2016
Grant date	Jun 21, 2016

Abstract

A device package includes a plurality of dies, a molding compound extending along sidewalls of the plurality of dies, and a polymer layer over and contacting the molding compound. The molding compound comprises a non-planar top surface, and a total thickness variation (TTV) of a top surface of the polymer layer is less than a TTV of the non-planar top surface of the molding compound. The device package further includes a conductive feature on the polymer layer, wherein the conductive feature is electrically connected at least one of the plurality of dies.

First claim

What is claimed is:

1. A device package comprising:
a plurality of dies;
a molding compound extending along sidewalls of the plurality of dies, wherein the molding compound comprises a non-planar top surface;
a polymer layer over and contacting the molding compound, wherein a total thickness variation (TTV) of a top surface of the polymer layer is less than a TTV of the non-planar top surface of the molding compound; and
a conductive feature on the polymer layer, wherein the conductive feature is electrically connected at least one of the plurality of dies.

2. The device package of claim 1 , wherein the non-planar top surface is disposed between adjacent ones of the plurality of dies, and wherein a portion of the polymer layer disposed on the non-planar top surface of the molding compound also comprises a non-planar top surface.

3. The device package of claim 2 , wherein a TTV of the portion of the polymer layer is less than about 15 micrometers (μm) when a spacing between the adjacent ones of the plurality of dies is less than about 3000 μm.

4. The device package of claim 2 , wherein a TTV of the portion of the polymer layer is less than about 10 micrometers (μm) when a spacing between the adjacent ones of the plurality of dies is less than about 500 μm.

5. The device package of claim 2 , wherein a TTV of the portion of the polymer layer is less than about 5 micrometers (μm) when a spacing between the adjacent ones of the plurality of dies is less than about 100 μm.

6. The device package of claim 1 , wherein the conductive feature comprises a non-planar top surface.

7. The device package of claim 1 , wherein the non-planar top surface of the molding compound is concave.

8. The device package of claim 1 , wherein the TTV of the non-planar top surface of the molding compound is about 5 μm to about 30 μm.

9. A device package comprising:
a first die;
a second die adjacent the first die;
a molding compound extending along sidewalls of the first die and the second die, wherein the molding compound comprises a non-planar top surface between the first die and the second die;
a polymer layer over and contacting the molding compound, wherein the polymer layer comprises a non-planar top surface over the non-planar top surface of the molding compound, and wherein the non-planar top surface of the polymer layer has a total thickness variation (TTV) less than about 5 micrometers (μm); and
a conductive line over the polymer layer, wherein at least a portion of the conductive line contacts the non-planar top surface of the polymer layer, and wherein the conductive line is electrically connected to the first die.

10. The device package of claim 9 , wherein a TTV of the non-planar top surface of the molding compound is greater than the TTV of the non-planar top surface of the polymer layer.

11. The device package of claim 10 , wherein the TTV of the molding compound is about 5 micrometers (μm) to about 30 μm.

12. The device package of claim 9 , wherein a spacing between the first die and the second die is less than about 3000 μm.

13. The device package of claim 9 , wherein the non-planar top surface of the polymer layer and the non-planar top surface of the molding compound comprise concave profiles.

14. The device package of claim 9 , wherein the portion of the conductive line contacting the non-planar top surface of the polymer layer comprises a non-planar top surface.

15. The device package of claim 9 further comprising a through intervia extending through the molding compound and the polymer layer, wherein the through intervia is electrically connected to conductive elements formed over the polymer layer.

16. A device comprising:
a first die;
a second die;
a molding compound between the first die and the second die, wherein a top surface of the molding compound is non-planar;
a continuous polymer layer over the first die, the second die, and the molding compound wherein a portion of the continuous polymer layer contacting the molding compound comprises a surface opposite the molding compound, and wherein the surface of the portion of the continuous polymer layer is more planar than the top surface of the molding compound; and
a conductive feature comprising:
a first portion contacting the surface of the portion of the continuous polymer layer; and
a second portion extending through the continuous polymer layer and electrically connected to the first die.

17. The device of claim 16 , wherein the first die and the second die are spaced less than 3000 μm apart.

18. The device of claim 16 , wherein a total thickness variation (TTV) of the top surface of the molding compound is about 5 micrometers (μm) to about 30 μm, and wherein a TTV of the surface of the portion of the continuous polymer layer is less than about 5 μm.

19. The device of claim 16 , wherein the first die comprises a contact pad and a passivation layer exposing the contact pad, and wherein the continuous polymer layer contacts the contact pad.

20. The device of claim 16 , wherein a surface of the first portion of the conductive feature opposite the continuous polymer layer is non-planar.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Yu Chen-Hua
• Liu Chung-Shi

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/9413

  on encapsulations · CPC title