Methods of manufacturing semiconductor devices

Patent metadata

Field	Value
Publication number	US-10141200-B2
Application number	US-201715613822-A
Country	US
Kind code	B2
Filing date	Jun 5, 2017
Priority date	Jul 6, 2016
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

In a method of manufacturing a semiconductor memory device, a plurality of first conductive structures including a first conductive pattern and a hard mask are sequentially stacked on a substrate. A plurality of preliminary spacer structures including first spacers, sacrificial spacers and second spacers are sequentially stacked on sidewalls of the conductive structures. A plurality of pad structures are formed on the substrate between the preliminary spacer structures, and define openings exposing an upper portion of the sacrificial spacers. A first mask pattern is formed to cover surfaces of the pad structures, and expose the upper portion of the sacrificial spacers. The sacrificial spacers are removed to form first spacer structures having respective air spacers, and the first spacer structures include the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of conductive structures on a substrate, each of the conductive structures including a first conductive pattern and a hard mask sequentially stacked;
forming a plurality of preliminary spacer structures on sidewalls of the conductive structures, respectively, the preliminary spacer structures including first spacers, sacrificial spacers and second spacers sequentially stacked;
forming a plurality of pad structures on the substrate between the preliminary spacer structures, respectively, the plurality of pad structures defining openings exposing upper portions of the sacrificial spacers;
forming a capping layer on surfaces of the pad structures;
forming a first mask pattern on the pad structures, the first mask pattern covering the surfaces of the pad structures and exposing the upper portions of the sacrificial spacers; and
removing the sacrificial spacers to form first spacer structures having respective air spacers, the first spacer structures including the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures.

2. The method as claimed in claim 1 , wherein the forming a first mask pattern includes:
forming a mask layer on an inner surface of the openings and upper surfaces of the pad structures, wherein a portion of the mask layer on the upper surfaces of the pad structures has a first thickness and a portion of the mask layer on a bottom surface of the opening has a second thickness less than the first thickness; and
etching the mask layer anisotropically to expose an upper surface of the sacrificial spacers.

3. The method as claimed in claim 2 , wherein the forming a mask layer includes a low pressure-chemical vapor deposition (LP-CVD) process.

4. The method as claimed in claim 1 , wherein the first mask pattern includes amorphous carbon.

5. The method as claimed in claim 1 , wherein the capping layer includes silicon nitride.

6. The method as claimed in claim 1 , further comprising:
forming a filling insulation layer on the air spacers to fill the openings after the forming first spacer structures.

7. The method as claimed in claim 1 , wherein the forming first spacer structures removes the sacrificial spacers by a wet etching process.

8. The method as claimed in claim 1 , wherein a bottom surface of the openings is lower than a top surface of each of the conductive structures.

9. The method as claimed in claim 1 , wherein the forming a plurality of pad structures includes:
forming first conductive patterns on the substrate between the preliminary spacer structures, wherein an upper surface of each of the first conductive patterns is lower than an upper surface of each of the conductive structures;
forming a second conductive layer on the first conductive patterns to cover each of the conductive structures; and
patterning the second conductive layer to form second conductive patterns covering upper portions of the conductive structures.

10. The method as claimed in claim 9 , wherein the second conductive layer includes a metal.

11. The method as claimed in claim 1 , after the forming first spacer structures, further comprising:
forming a second mask pattern on upper sidewalls of the first and second spacers, an inner surface of the openings and the pad structures, wherein the air spacers are not covered by the second mask pattern;
etching sidewalls of the first and second spacers using the second mask pattern to form third and fourth spacers, respectively;
forming second spacer structures by forming liner layers on surfaces of the third and fourth spacers and the openings, the second spacer structures including the third spacers, the fourth spacers, the liner layers and the air spacers; and
forming a filling insulation layer on the liner layers to fill the openings by an atomic layer deposition (ALD) process.

12. A method of manufacturing a semiconductor device, the method comprising:
forming a plurality of conductive structures on a substrate, each of the conductive structures including a first conductive pattern and a hard mask sequentially stacked;
forming a plurality of first preliminary spacer structures on sidewalls of the conductive structures, the first preliminary spacer structures including first spacers, sacrificial spacers and second spacers sequentially stacked;
forming a plurality of pad structures on the substrate between the first preliminary spacer structures, the plurality of pad structures defining openings exposing an upper portion of the sacrificial spacers;
forming a plurality of second preliminary spacer structures by removing the sacrificial spacers to form air spacers, the second preliminary spacer structures including the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the conductive structures;
forming a mask pattern on upper sidewalls of the first and second spacers, an inner surface of the openings and the pad structures, wherein the air spacers are not covered by the mask pattern;
etching sidewalls of the first and second spacers using the mask pattern to form third and fourth spacers, respectively;
forming spacer structures by forming a liner layer on surfaces of the third and fourth spacers and the openings, the spacer structures including the third spacers, the fourth spacers, the liner layers and the air spacers; and
forming a filling insulation layer on the liner layers to fill the openings.

13. The method as claimed in claim 12 , wherein each of the liner layers and the filling insulation layer include silicon nitride.

14. The method as claimed in claim 12 , wherein each of the liner layers and the filling insulation layer is formed by an atomic layer deposition (ALD) process.

15. A method comprising:
forming a first conductive pattern on a substrate;
forming first spacer structures on sidewalls of the first conductive pattern, respectively, each of the first spacer structures including a sacrificial spacer between respective first and second spacers;
forming a second conductive pattern on the substrate between the first spacer structures;
forming a third conductive pattern on the second conductive pattern, the third conductive pattern defining openings exposing the respective sacrificial spacers; and
forming second spacer structures by removing the sacrificial spacers to form air spacers between the respective first and second spacers, the second spacer structures including the first spacers, the air spacers and the second spacers sequentially stacked on the sidewalls of the first conductive pattern.

16. The method as claimed in claim 15 , further comprising:
forming a filling insulation layer on a top portion of the air spacers to fill the openings after the forming second spacer structures.

17. The method as claimed in claim 15 , wherein the forming second spacer structures removes the sacrificial spacers by a wet etching process.

18. The method as claimed in claim 15 , wherein a bottom surface of the openings is lower than a top surface of the first conductive pattern.

19. The method as claimed in claim 15 , further comprising:
forming a mask layer on an inner surface of the openings and an upper surface of the third conductive pattern by a low pressure-chemical vapor deposition (LP-CVD) process; and
etching the mask layer anisotropically to form a mask pattern exposing the sacrificial spacers, the mask pattern including amorp

Assignees

• Samsung Electronics Co Ltd

Inventors

• Byun Kyung-Mun
• Im Badro
• Kim Hong-Rae
• DO Sin-Hae
• Park Gyeong-Deok

Classifications

• H10P72/0444

  Apparatus for wiring semiconductor or solid-state device · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P14/43

  Chemical deposition, e.g. chemical vapour deposition [CVD] · CPC title

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D64/01328

  by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall · CPC title