Method of fabricating spacers in a strained semiconductor device

Patent metadata

Field	Value
Publication number	US-9419099-B2
Application number	US-201514688720-A
Country	US
Kind code	B2
Filing date	Apr 16, 2015
Priority date	Mar 31, 2009
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a silicon substrate;
a gate structure formed over the silicon substrate, wherein the gate structure includes a high-k gate dielectric, a metal gate electrode formed over the high-k gate dielectric, and first and second oxide-nitrogen-oxide (ONO) gate spacers formed on opposite sidewalls of the gate dielectric and gate electrode;
first and second silicon compound components formed in the silicon substrate and on opposite sides of the gate structure, wherein one of the first and second silicon compound components has a slanted surface that borders a dielectric trench isolation structure, and wherein the other of the first and second silicon compound components has a horizontal surface substantially parallel to a surface of the silicon substrate over which the gate structure is formed; and
first and second source/drain regions formed in the first and second silicon compound components, respectively.

2. The semiconductor device of claim 1 , wherein the first and second ONO gate spacers each include a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer, the silicon nitride layer being disposed between the first silicon oxide layer and the second silicon oxide layer.

3. The semiconductor device of claim 2 , wherein:
the first silicon oxide layer is bordering the high-k gate dielectric and the gate electrode; and
the second silicon oxide layer has a curved profile and is thicker than the first silicon oxide layer.

4. The semiconductor device of claim 1 , wherein: the first and second silicon compound components each contain silicon germanium or silicon carbide.

5. The semiconductor device of claim 1 , wherein the first and second ONO gate spacers are aligned with the first and second silicon compound components, respectively.

6. The semiconductor device of claim 1 , wherein the silicon substrate and the first and second silicon compound components contain different types of semiconductor materials.

7. The semiconductor device of claim 1 , wherein at least one of the first and second source/drain regions has the slanted surface.

8. The semiconductor device of claim 7 , wherein the at least one of the first and second source/drain regions having the slanted surface is bordering the dielectric trench isolation structure.

9. A semiconductor device, comprising:
a substrate containing a plurality of silicon compound component regions in the substrate, each of the plurality of silicon compound component regions including a profile defined by a linear surface and an arc extending from a first end of the linear surface to a second end of the linear surface;
a gate disposed over the substrate, wherein the gate is disposed between two of the silicon compound component regions; and
a multi-layered gate spacer disposed on a sidewall of the gate, wherein the gate spacer includes a first layer containing a first material disposed between a second layer and a third layer each containing a second material different from the first material;
wherein only one of the silicon compound component regions disposed adjacent to the gate has a slanted surface and is bordered on a first side by the multi-layered gate spacer and on a second side by a dielectric trench isolation structure.

10. The semiconductor device of claim 9 , wherein:
the first layer contains a nitride material as the first material; and
the second layer and the third layer each contain an oxide material as the second material.

11. The semiconductor device of claim 9 , wherein an outer edge of the gate spacer is substantially aligned with one of the silicon compound component regions.

12. The semiconductor device of claim 9 , wherein the substrate and the silicon compound component regions contain different types of semiconductor materials.

13. The semiconductor device of claim 12 , wherein:
the substrate contains silicon; and
the silicon compound component regions contain one of silicon germanium and silicon carbide.

14. A semiconductor device, comprising:
a silicon substrate having a silicon region, silicon compound component regions disposed on either side of the silicon region, and shallow trench isolation regions, wherein one and not the other of the silicon compound component regions is interposed between and borders each of the silicon region and a shallow trench isolation region, and wherein the silicon compound component regions include an isotropic profile; and

a transistor including:
a gate stack formed over the silicon region;

oxide-nitride-oxygen (ONO) spacers formed on sidewalls of the gate stack, wherein each ONO spacer includes a nitride layer sandwiched between a first oxide layer and a second oxide layer; and
lightly doped source/drain (LDD) regions each formed in a portion of the silicon region underneath the ONO spacer and in a portion of the silicon compound component region.

15. The device of claim 14 , wherein the gate stack includes:
a high-k dielectric layer formed over the silicon region;
a metal layer formed over the high-k dielectric layer; and
a polysilicon layer formed over the metal layer.

16. The semiconductor device of claim 14 , wherein the silicon compound component region includes silicon germanium or silicon carbide.

17. The semiconductor device of claim 16 , wherein the one and not the other of the silicon compound component regions is interrupted by the shallow trench isolation region such that the one of the silicon compound component regions has a slanted surface.

18. The semiconductor device of claim 14 , wherein the first oxide layer includes a thickness ranging from about 30 angstroms to about 200 angstroms;
wherein the nitride layer includes a thickness ranging from about 30 angstrom to about 200 angstroms;
wherein the second oxide layer includes a thickness ranging from about 100 angstroms to about 1000 angstroms; and
wherein the first oxide layer is disposed on the sidewall of the gate stack.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsu Chen-Pin
• Chuang Harry
• Thei Kong-Beng

Classifications

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title