Closepath fast incremented sum in a three-path fused multiply-add design

Patent metadata

Field	Value
Publication number	US-10140092-B2
Application number	US-201715430438-A
Country	US
Kind code	B2
Filing date	Feb 10, 2017
Priority date	Nov 4, 2016
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

According to one general aspect, an apparatus may include a floating-point multiply-accumulate unit configured to generate a floating point result by either adding or subtracting three floating point operands: an addend, a product carry, and a product sum. The floating-point multiply-accumulate unit may include a close path adder. The close path adder may include an unincremented mantissa addition circuit configured to compute an unincremented mantissa result based upon the three floating point operands. The close path adder may also include an incremented mantissa addition circuit configured to, at least partially in parallel with the mantissa addition circuit, produce an incremented mantissa result. The close path adder may further include a selection circuit configured to produce a close path result by selecting between the unincremented mantissa result and the incremented mantissa result.

First claim

What is claimed is:

1. An apparatus comprising:
a floating-point multiply-accumulate unit configured to generate a floating point result by either adding or subtracting three floating point operands: an addend, a product carry, and a product sum; and comprising:
a close path adder comprising:
an unincremented mantissa addition circuit configured to compute an unincremented mantissa result based upon the three floating point operands;
an incremented mantissa addition circuit configured to, at least partially in parallel with the unincremented mantissa addition circuit, produce an incremented mantissa result; and
a selection circuit configured to produce a close path result by selecting between the unincremented mantissa result and the incremented mantissa result.

2. The apparatus of claim 1 , wherein the incremented mantissa addition circuit is configured to, in parallel with the unincremented mantissa addition circuit, produce an incremented mantissa result even though an incrementing point of the unincremented mantissa result is not known when the incremented mantissa addition circuit produces the incremented mantissa result.

3. The apparatus of claim 1 , wherein the close path adder comprises:
a compressor to produce, based upon the addend, the product carry and the product sum, a result carry and a result sum.

4. The apparatus of claim 3 , wherein the incremented mantissa addition circuit comprises:
a leading zero anticipator to compute an increment amount; and
an adder to add the result carry, the result sum, and the increment amount to produce an unnormalized incremented mantissa result.

5. The apparatus of claim 1 , wherein the incremented mantissa addition circuit comprises:
a leading zero anticipator configured to compute a first least-significant-bit (LSB) mask and a second least-significant-bit (LSB) mask.

6. The apparatus of claim 5 , wherein the incremented mantissa addition circuit comprises a rounding circuit configured to:
compute an LSB and a rounding bit based, at least in part, upon the first LSB mask, and
compute a sticky bit based, at least in part, upon the second LSB mask.

7. The apparatus of claim 5 , wherein the leading zero anticipator is configured to compute the first LSB mask and the second LSB mask, in parallel with the production of the incremented mantissa result.

8. The apparatus of claim 1 , wherein the selection circuit comprises:
a normalizer circuit to normalize an unnormalized incremented mantissa result and an unnormalized unincremented mantissa result; and
a sum selection circuit to select between the incremented mantissa result and the unincremented mantissa result.

9. A system comprising:
a memory configured to store floating point operands; and
a processor comprising
a floating-point multiply-accumulate unit configured to generate a floating point result by either adding or subtracting three floating point operands: an addend, a product carry, and a product sum; and comprising:
a close path adder comprising:
an unincremented mantissa addition circuit configured to compute an unincremented mantissa result based upon the three floating point operands;
an incremented mantissa addition circuit configured to, at least partially in parallel with the unincremented mantissa addition circuit, produce an incremented mantissa result; and
a selection circuit configured to produce a close path result by selecting between the unincremented mantissa result and the incremented mantissa result.

10. The system of claim 9 , wherein the incremented mantissa addition circuit is configured to, in parallel with the unincremented mantissa addition circuit, produce an incremented mantissa result even though an incrementing point of the unincremented mantissa result is not known when the incremented mantissa addition circuit produces the incremented mantissa result.

11. The system of claim 9 , wherein the close path adder comprises:
a compressor to produce, based upon the addend, the product carry and the product sum, a result carry and a result sum.

12. The system of claim 11 , wherein the incremented mantissa addition circuit comprises:
a leading zero anticipator to compute an increment amount; and
an adder to add the result carry, the result sum, and the increment amount to produce an unnormalized incremented mantissa result.

13. The system of claim 9 , wherein the incremented mantissa addition circuit comprises:
a leading zero anticipator configured to compute a first least-significant-bit (LSB) mask and a second least-significant-bit (LSB) mask.

14. The system of claim 13 , wherein the incremented mantissa addition circuit comprises a rounding circuit configured to:
compute an LSB and a rounding bit based, at least in part, upon the first LSB mask, and
compute a sticky bit based, at least in part, upon the second LSB mask.

15. The system of claim 13 , wherein the leading zero anticipator is configured to compute the first LSB mask and the second LSB mask, in parallel with the production of the incremented mantissa result.

16. The system of claim 9 , wherein the selection circuit comprises:
a normalizer circuit to normalize an unnormalized incremented mantissa result and an unnormalized unincremented mantissa result; and
a sum selection circuit to select between the incremented mantissa result and the unincremented mantissa result.

17. A method comprising:
receiving three floating point operands: an addend, a product carry, and a product sum;
computing, via an unincremented mantissa addition circuit, an unincremented mantissa result based upon the three floating point operands;
computing, by an incremented mantissa addition circuit and at least partially in parallel with the unincremented mantissa addition circuit, an incremented mantissa result; and
producing a close path result by selecting between the unincremented mantissa result and the incremented mantissa result.

18. The method of claim 17 , wherein computing an incremented mantissa result comprises:
generating, based upon the addend, the product carry and the product sum, a result carry and a result sum; and
computing the incremented mantissa result based, at least in part upon, the result carry, the result sum, and an output of a leading zero anticipator.

19. The method of claim 17 , wherein computing an incremented mantissa result comprises:
computing compute a first least-significant-bit (LSB) mask and a second least-significant-bit LSB) mask; and
computing an LSB and a rounding bit based, at least in part, upon the first LSB mask, and computing a sticky bit based, at least in part, upon the second LSB mask.

20. The method of claim 19 , wherein computing an incremented mantissa result comprises:
computing the first LSB mask and the second LSB mask, in parallel with the production of the incremented mantissa result.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahmed Ashraf

Classifications

• G06F7/4876

  Multiplying · CPC title

• G06F7/485 Primary

  Adding; Subtracting {(G06F7/4833, G06F7/4836 take precedence)} · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title