Voltage and temperature compensated device for physically unclonable function

Patent metadata

Field	Value
Publication number	US-10135615-B2
Application number	US-201615151913-A
Country	US
Kind code	B2
Filing date	May 11, 2016
Priority date	May 11, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

Systems and methods for providing assistance for performing a physically unclonable function (PUF) are provided. Disclosed systems can include a PUF bitcell including at least two voltage-compensated proportional-to-absolute (PTAT) generators, each of which can be configured to generate a first voltage and a second voltage that is different from the first voltage by a voltage difference. The voltage difference can be resistant to temperature variations and variations, if any, in the supply voltage. The system can further include a comparator, which can be electrically coupled to each of the at least two PTAT generators, and can be configured to receive the first voltage and the second voltage generated therefrom, determine a polarity of each of the voltage differences, and generate a random bit.

First claim

What is claimed is:

1. A system for performing a physically unclonable function (PUF) using a supply voltage, comprising:
a PUF bitcell comprising at least two voltage-compensated proportional-to-absolute (PTAT) generators, each configured to generate a first voltage and a second voltage that is different from the first voltage by a voltage difference, wherein the voltage difference is resistant to temperature variations and variations, if any, in the supply voltage and wherein the voltage difference is a function of mismatch between threshold voltages of the at least two PTAT generators; and
a comparator, electrically coupled to each of the at least two PTAT generators, configured to receive the first voltage and the second voltage generated therefrom, determine a polarity of each of the voltage differences, and generate, based on the polarity, a random bit that is resistant to variations in temperature and voltage.

2. The system of claim 1 , wherein each of the at least two PTAT generators comprises a bandgap circuit comprising a first diode and a second diode that operate at different current densities, and wherein the first diode generates the first voltage and the second diode generates the second voltage.

3. The system of claim 2 , wherein the difference of the first voltage and the second voltage is based on threshold voltage mismatch between the first diode and the second diode.

4. The system of claim 1 , wherein the voltage difference defines a current that is proportional to absolute temperature and wherein the current is mirrored to a resistor across P-type current sources.

5. The system of claim 1 , wherein the PUF bitcell comprises a header pair and a footer pair, wherein the header pair and the footer pair each comprise a pair of PTAT generators.

6. The system of claim 5 , wherein the voltage difference of each pair of PTAT generators is based on threshold voltages of the header pair and the footer pair.

7. The system of claim 6 , wherein the voltage difference is a random variable with a zero mean and a standard deviation that that is based on standard deviations of threshold voltage fluctuations of the header pair and the footer pair.

8. A system for performing a physically unclonable function (PUF) using a supply voltage, comprising:
an array of PUF bitcells, each comprising:
at least two voltage-compensated proportional-to-absolute (PTAT) generators, each configured to generate a first voltage and a second voltage that is different from the first voltage by a voltage difference, wherein the voltage difference is resistant to temperature variations and variations, if any, in the supply voltage and wherein the voltage difference is a function of mismatch between threshold voltages of the at least two PTAT generators; and

a voltage comparator, electrically coupled to each of the at least two PTAT generators, configured to receive the first voltage and the second voltage generated therefrom, determine a polarity of each of the voltage differences, and generate, based on the polarity, a random bit that is resistant to variations in temperature and voltage.

9. The system of claim 8 , wherein each column of the array comprises a cascode device to improve supply voltage stability.

10. The system of claim 8 , wherein a capacitor is added to each differential input of the voltage comparator to minimize kick-back noise.

11. The system of claim 8 , wherein the at least two PTAT generators comprises a bandgap circuit comprising a first diode and a second diode that operate at different current densities, and wherein the first diode generates the first voltage and the second diode generates the second voltage.

12. The system of claim 8 , wherein the difference of the first voltage and the second voltage is based on threshold voltage mismatch between the first diode and the second diode.

13. The system of claim 8 , wherein the voltage difference defines a current that is proportional to absolute temperature and wherein the current is mirrored to a resistor across P-type current sources.

14. The system of claim 8 , wherein each PUF bitcell comprises a header pair and a footer pair wherein the header pair and the footer pair each comprise a pair of PTAT generators.

15. The system of claim 14 , wherein the header pair of each PUF bitcell is upsized and laid out in a common centroid layout to minimize threshold voltage mismatch.

16. The system of claim 14 , wherein the voltage difference of each pair of PTAT generators is based on threshold voltages of the header pair and the footer pair.

17. The system of claim 16 , wherein the voltage difference is a random variable with a zero mean and a standard deviation that is based on standard deviations of threshold voltage fluctuations of the header pair and the footer pair.

18. The system of claim 8 , wherein a plurality of voltage differences is generated from the array, each voltage difference of the plurality of voltage difference associated with a bitcell in the array, and wherein the voltage compator is configured to generate the random bit by applying a temporal majority voting scheme to each of a plurality of polarities of the plurality of voltage differences.

Assignees

• Univ Columbia

Inventors

• Seok Mingoo
• Li Jiangyi

Classifications

• H04L9/0869 Primary

  involving random numbers or seeds · CPC title

• H04L9/0866 Primary

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title