FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage

Patent metadata

Field	Value
Publication number	US-8941405-B2
Application number	US-201213566805-A
Country	US
Kind code	B2
Filing date	Aug 3, 2012
Priority date	Aug 3, 2012
Publication date	Jan 27, 2015
Grant date	Jan 27, 2015

Abstract

A FET pair based physically unclonable function (PUF) circuit with a constant common mode voltage and methods of use are disclosed. The circuit includes a first n-type field effect transistor (NFET) and a second NFET. The circuit also includes a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET) and a second load resistor coupled to the second NFET by a second PFET. The circuit further comprises a closed loop, wherein the closed loop creates a constant common mode voltage.

First claim

What is claimed is:

1. A structure, comprising:
a physically unclonable function (PUF) sensor array; and
a differential amplifier coupled to the PUF sensor array,
wherein the differential amplifier coupled to the PUF sensor array creates a closed loop circuit; and
wherein the closed loop comprises the differential amplifier coupled to a connection point of a plurality of resistors, and the plurality of resistors are coupled to each other such that the connection point of the plurality of resistors form a common mode voltage.

2. The structure of claim 1 , wherein the closed loop circuit further comprises:
a plurality of voltage followers coupled to the PUF sensor array; and
the plurality of resistors connected to a respective output of the plurality of voltage followers.

3. The structure of claim 2 , wherein:
the common mode voltage and a reference voltage are provided to the differential amplifier as inputs; and
an output of the differential amplifier is provided as a gate voltage or a power supply voltage of the PUF sensor array.

4. The structure of claim 3 , wherein the output of the differential amplifier is provided to one or more gates of the PUF sensor array.

5. The structure of claim 4 , wherein the output of the differential amplifier tunes a gate voltage of the PUF sensor array, such that the PUF sensor array has a constant common mode voltage.

6. The structure of claim 5 , wherein the tuned gate voltage reduces a standard deviation of the constant common mode voltage.

7. The structure of claim 5 , wherein the standard deviation is 0.003 volts.

8. The structure of claim 3 , wherein the output of the differential amplifier is coupled to the power supply voltage connected to the PUF sensor array.

9. The structure of claim 8 , wherein the output of the differential amplifier tunes the power supply voltage, such that the PUF sensor array has a constant common mode voltage.

10. A structure, comprising:
a physically unclonable function (PUF) sensor array, wherein the PUF sensor array has a constant common mode voltage, which reduces voltage variations and improves reliability of an output of the PUF sensor array; and
a differential amplifier coupled to the PUF sensor array, wherein the differential amplifier coupled to the PUF sensor array creates a closed loop circuit.

11. A circuit, comprising:
a first n-type field effect transistor (NFET);
a second NFET;
a first load resistor coupled to the first NFET by a first p-type field effect transistor (PFET);
a second load resistor coupled to the second NFET by a second PFET; and
a closed loop,
wherein the closed loop creates a constant common mode voltage; and
wherein the closed loop comprises:
a plurality of voltage followers respectively coupled to a drain of the first NFET by the first PFET and a drain of the second NFET by the second PFET; and
a plurality of resistors connected to a respective output of the plurality of voltage followers, wherein:
a connection of the plurality of resistors are coupled to each other and is provided to the differential amplifier as a first input; and
a reference voltage is provided to the differential amplifier as a second input.

12. The circuit of claim 11 , wherein the constant common mode voltage is driven to the reference voltage.

13. The circuit of claim 12 , wherein the output of the differential amplifier is provided to a gate of the first NFET and a gate of the second NFET.

14. The circuit of claim 12 , wherein:
the output of the differential amplifier is coupled to a power supply voltage; and
the power supply voltage is coupled to the first load resistor and the second load resistor.

15. A method, comprising:
creating a closed loop circuit;
driving a common mode voltage to a reference voltage; and
creating a constant common mode voltage,
wherein creating the constant common mode voltage reduces common mode voltage variations and improves reliability of an output of a physically unclonable function (PUF) sensor.

16. The method of claim 15 , wherein creating the closed loop circuit comprises providing an output of a differential amplifier as a gate voltage to a plurality of transistors or coupling the output of the differential amplifier to a power supply voltage.

17. The method of claim 16 , wherein creating the constant common mode voltage comprises tuning the gate voltage.

18. The method of claim 16 , wherein creating the constant common mode voltage comprising tuning the power supply voltage.

Assignees

• Chi Howard H
• Dai Haitao O
• Feng Kai D
• Papae Donald J
• IBM

Inventors

• Chi Howard H
• Dai Haitao O
• Feng Kai D
• Papae Donald J

Classifications

• G06F7/588 Primary

  Random number generators, i.e. based on natural stochastic processes · CPC title

• G09C1/00

  Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) · CPC title

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• H04L9/3278

  using physically unclonable functions [PUF] · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title