Electrostatic discharge protection circuit applied in integrated circuit

Patent metadata

Field	Value
Publication number	US-10134725-B2
Application number	US-201715813179-A
Country	US
Kind code	B2
Filing date	Nov 15, 2017
Priority date	Sep 26, 2016
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

The present application provides an electrostatic discharge protection circuit including a first N-type transistor, a second N-type transistor and a high-voltage tracing circuit. The high-voltage tracing circuit includes a first input terminal, a second input terminal and an output terminal. The first input terminal is coupled to the metal pad to receive a metal pad voltage. The second input terminal receives a supply voltage. The output terminal is coupled to the second N-type transistor and configured to output a high-voltage tracing voltage, wherein the high-voltage tracing voltage is larger than or equal to the metal pad voltage.

First claim

What is claimed is:

1. An electrostatic discharge (ESD) protection circuit, comprising:
a first N-type transistor, comprising:
a first gate terminal, coupled to a ground terminal;
a first electrode terminal, coupled to the first gate terminal; and
a second electrode terminal;

a second N-type transistor, comprising:
a second gate terminal, coupled to a metal pad;
a third electrode terminal, coupled to the second gate terminal;
a fourth electrode terminal, coupled to the second electrode terminal; and
a fifth electrode terminal; and

a high-voltage tracing circuit, comprising:
a first input terminal, coupled to the metal pad and configured to receive a metal pad voltage;
a second input terminal, configured to receive a supply voltage; and
an output terminal, coupled to the fifth electrode terminal, configured to output a high-voltage tracing voltage, wherein the high-voltage tracing voltage is larger than or equal to the metal pad voltage.

2. The ESD protection circuit as claim 1 , wherein the high-voltage tracing circuit comprises:
a first transistor, comprising:
a first control terminal, coupled to the second input terminal;
a first terminal, coupled to the first input terminal; and
a second terminal, coupled to the output terminal; and

a second transistor, comprising:
a second control terminal, coupled to the first input terminal;
a third terminal, coupled to the second input terminal; and
a fourth terminal, coupled to the output terminal.

3. The ESD protection circuit as claim 2 , wherein when the metal pad voltage is larger than the supply voltage, the first transistor is conducted and the second transistor is cutoff; or when the metal pad voltage is less than the supply voltage, the first transistor is cutoff and the second transistor is conducted.

4. The ESD protection circuit as claim 2 , wherein the high-voltage tracing circuit further comprises:
a diode, coupled between the first input terminal and the first terminal of the first transistor.

5. The ESD protection circuit as claim 1 , wherein the first N-type transistor further comprises:
a first base terminal, coupled to the first electrode terminal.

6. The ESD protection circuit as claim 1 , wherein the second N-type transistor comprises:
a first deep N-well, disposed under the third electrode terminal, the fourth electrode terminal and the fifth electrode terminal.

7. The ESD protection circuit as claim 6 , wherein the second N-type transistor further comprises a first P-well, disposed between the third electrode terminal, the fourth electrode terminal and the first deep N-well.

8. The ESD protection circuit as claim 7 , wherein the second N-type transistor further comprises a first N-well, and the first N-well is disposed by a side of the first P-well.

9. The ESD protection circuit as claim 8 , wherein the second N-type transistor further comprises an N-type region, the N-type region is disposed in the first N-well and is formed as the fifth electrode terminal.

10. The ESD protection circuit as claim 1 , wherein:
when a metal pad voltage of the metal pad is a positive ESD voltage, a first current flows to the ground terminal through the first N-type transistor or the first N-type transistor is formed as a first bipolar transistor; or
when a metal pad voltage of the metal pad is a negative ESD voltage, a second current flows to the metal pad through the second N-type transistor, or the second N-type transistor is formed as a second bipolar transistor.

11. The ESD protection circuit as claim 10 , wherein the positive ESD voltage is larger than 1 kilovolt, or the negative ESD voltage is less than negative 1 kilovolt.

12. The ESD protection circuit as claim 1 , wherein the high-voltage tracing voltage is a maximum voltage of the metal pad voltage and the supply voltage.

13. The ESD protection circuit as claim 1 , further comprising:
a diode, coupled between the fifth electrode terminal of the second N-type transistor and the output terminal of the high-voltage tracing circuit.

14. The ESD protection circuit as claim 13 , wherein the diode comprises:
a first terminal, coupled to the fifth electrode terminal of the second N-type transistor; and
a second terminal, coupled to the output terminal of the high-voltage tracing circuit.

15. The ESD protection circuit as claim 14 , wherein the diode comprises:
a second N-well, disposed under the first terminal and the second terminal.

16. The ESD protection circuit as claim 14 , wherein the diode comprises:
a second P-well, disposed under the first terminal and the second terminal.

17. The ESD protection circuit as claim 16 , wherein the diode further comprises:
a second deep N-well, disposed under the second P-well.

18. The ESD protection circuit of claim 1 , further comprising:
a plurality of diodes, formed as a diode series;
wherein the diode series is coupled between the fifth electrode terminal of the second N-type transistor and the output terminal of the high-voltage tracing circuit.

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Lee Tsung-Lung

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H01L27/0722

  Electricity · mapped topic

• H01L27/0288

  Electricity · mapped topic

• H01L21/761

  Electricity · mapped topic