Process for smoothing the surface of a structure

Patent metadata

Field	Value
Publication number	US-10134602-B2
Application number	US-201715403505-A
Country	US
Kind code	B2
Filing date	Jan 11, 2017
Priority date	Jan 14, 2016
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A process for smoothing a silicon-on-insulator structure comprising the exposure of a surface of the structure to an inert or reducing gas flow and to a high temperature during a heat treatment includes performing a first heat treatment step at a first temperature and under a first gas flow defined by a first flow rate, and performing a second heat treatment step at a second temperature lower than the first temperature and under a second gas flow defined by a second flow rate lower than the first flow rate.

First claim

What is claimed is:

1. A method for smoothing a silicon-on-insulator structure comprising the exposure of a surface of the structure to an inert or reducing gas flow and to a high temperature during a heat treatment, the method comprising:
a first heat treatment step at a first temperature greater than a threshold temperature which is between 1150° C. and 1170° C., and under a first gas flow defined by a first flow rate greater than 20 slm; and
a second heat treatment step at a second temperature lower than the first temperature and the threshold temperature and greater than 1130° C., and under a second gas flow defined by a second flow rate lower than the first flow rate and less than 15 slm.

2. The method of claim 1 , further comprising a preliminary step of supplying the SOI structure comprising a thin surface layer positioned on a dielectric layer, the dielectric layer positioned on a carrier substrate, the surface layer having a thickness of less than 500 nm.

3. The method of claim 1 , wherein the first temperature is between 1160° C. and 1200° C.

4. The method of claim 3 , wherein the first temperature is between 1170° C. and 1200° C.

5. The method of claim 1 , wherein the second temperature is between 1130° C. and 1160° C.

6. The method of claim 1 , wherein the second heat treatment step comprises a hold at the second temperature of a given duration.

7. The method of claim 6 , wherein the duration of the hold is between 5 minutes and 2 hours.

8. The method of claim 1 , wherein the second heat treatment step comprises a temperature decrease ramp, starting from the second temperature, at a decrease ramp rate of between 0.1°/minute and 20°/minute.

9. The method of claim 1 , wherein the second flow rate is about 5 slm.

10. The method of claim 9 , wherein the inert gas is selected from argon or a mixture of argon and hydrogen.

11. The method of claim 1 , wherein the first heat treatment step and second heat treatment step are linked together during the same heat treatment.

12. The method of claim 1 , wherein the first temperature is greater than a threshold temperature and the second temperature is lower than the threshold temperature, the threshold temperature being between 1150° C. and 1170° C.

13. The method of claim 1 , wherein the second temperature is between 1130° C. and 1170° C.

14. The method of claim 1 , wherein the second heat treatment step comprises a hold at the second temperature of a given duration.

15. The method of claim 1 , wherein the first flow rate is greater than 20 slm, and wherein the second flow rate is less than 15 slm.

16. The method of claim 1 , wherein the inert gas is selected from argon or a mixture of argon and hydrogen.

17. The method of claim 1 , wherein the first heat treatment step and second heat treatment step are linked together during the same heat treatment.

18. The method of claim 1 , wherein the surface of the structure is smoothened and dissolution of an insulator layer occurs during the first heat treatment.

Assignees

• Soitec Silicon On Insulator

Inventors

• Landru Didier
• Kononchuk Oleg
• David Carole

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P90/1916

  with separation or delamination along an ion implanted layer, e.g. Smart-cut · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P95/906 Primary

  for altering the shape of semiconductors, e.g. smoothing the surface · CPC title

• H10P90/1906 Primary

  Preparing SOI wafers · CPC title