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US-2024055265-A1 · Feb 15, 2024 · US
Process to dissolve the oxide layer in the peripheral ring of a structure of semiconductor-on-insulator type
US9136113B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9136113-B2 |
| Application number | US-201314044846-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 2, 2013 |
| Priority date | Jan 22, 2009 |
| Publication date | Sep 15, 2015 |
| Grant date | Sep 15, 2015 |
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Abstract
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A process for avoiding formation of an Si—SiO 2 —H 2 environment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of a semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconductor material by performing a creep thermal treatment; and performing an oxide dissolution treatment to reduce part of the thickness of the oxide layer. In this process, the semiconductor material that encapsulates the oxide layer has a thickness before the oxide dissolution that is at least twice that of the oxide that is to be dissolved, thus avoiding formation of an Si—SiO 2 —H 2 environment on the peripheral ring where the oxide layer would otherwise be exposed.
First claim
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What is claimed is: 1. A process for avoiding formation of an Si—SiO 2 —H 2 environment during a dissolution treatment of a semiconductor-on-insulator structure, which process comprises: providing a semiconductor-on-insulator structure successively comprising a carrier substrate, an oxide layer, a thin layer of semiconductor material and a peripheral ring in which the oxide layer is exposed, the thin layer of semiconductor having a thickness that is less than 500 nm, the thicknes…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9136113B2 cover?
- A process for avoiding formation of an Si—SiO 2 —H 2 environment during a dissolution treatment of a semiconductor-on-insulator structure that includes a carrier substrate, an oxide layer, a thin layer of a semiconductor material and a peripheral ring in which the oxide layer is exposed. This process includes encapsulating at least the exposed oxide layer of the peripheral ring with semiconduc…
- Who is the assignee on this patent?
- Soitec Silicon On Insulator
- What technology area does this patent fall under?
- Primary CPC classification H10P95/906. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).