Memory system with multiple channel interfaces and method of operating same

Patent metadata

Field	Value
Publication number	US-10133298-B2
Application number	US-201614995834-A
Country	US
Kind code	B2
Filing date	Jan 14, 2016
Priority date	Apr 7, 2015
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.

First claim

What is claimed is:

1. A memory system, comprising:
a memory controller comprising a plurality of channel interfaces including a first channel interface and a second channel interface;
a plurality of memories including a first memory group and a second memory group; and
a plurality of channels including a first channel connected to the first memory group and a second channel connected to the second memory group,
wherein the first channel interface comprises:
a first clock modulator that receives a first input clock and applies a first modulation to the first input clock to generate a first slave clock;
a first first-in-first-out (FIFO) buffer that receives and stores a first control, address and/or data (CAD) signal; and
a first transmitter/receiver (Tx/Rx) that receives the first CAD signals from the FIFO buffer and synchronously controls communication of the first CAD signals to the first memory group via the first channel in response to the first slave clock, and
wherein the second channel interface comprises:
a second clock modulator that receives a second input clock and applies a second modulation, different than the first modulation, to the second input clock to generate a second slave clock, different from the first slave clock;
a second FIFO buffer that receives and stores at least one of second CAD signals; and
a second Tx/Rx that receives the second CAD signals from the second FIFO buffer and synchronously controls communication of the second CAD signals to the second memory group via the second channel in response to the second slave clock.

2. The memory system of claim 1 , wherein the memory controller further comprises a master clock generator that generates a master clock, and
each one of the first input clock and second input clock is the master clock as commonly applied to the first channel interface and second channel interface.

3. The memory system of claim 1 , wherein at least one memory in each of the first memory group and second memory group is a flash memory comprising a plurality of flash memory chips.

4. The memory system of claim 2 , wherein transition points for the first CAD signals are skewed in time with respect to transition points for the second CAD signals.

5. The memory system of claim 2 , wherein application of the first modulation to the first input clock includes applying up to a first phase shift to the first input clock, and application of the second modulation to the second input clock includes applying up to a second phase shift to the second input clock, wherein the first phase shift is different from the second phase shift.

6. The memory system of claim 1 , wherein the memory controller further comprises:
a master clock generator that generates a master clock applied to the first channel interface as the first input clock, and
the first slave clock generated from the first input clock by the first clock modulator is provided to the second channel interface as the second input clock.

Assignees

• Cho Young Jin
• Park Jae Geun
• Yoo Young Kwang
• Hwang Soon Suk
• Samsung Electronics Co Ltd

Inventors

• Cho Young-Jin
• Park Jae-Geun
• Yoo Young-Kwang
• Hwang Soon-Suk

Classifications

• G06F5/06

  for changing the speed of data flow, i.e. speed regularising {or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor (G06F7/78 takes precedence)} · CPC title

• G06F1/04

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• G11C16/3431 Primary

  Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step · CPC title

• G11C16/3422

  Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem · CPC title