Process condition based dynamic defect inspection

US10133263B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-10133263-B1
Application numberUS-201514829503-A
CountryUS
Kind codeB1
Filing dateAug 18, 2015
Priority dateAug 18, 2014
Publication dateNov 20, 2018
Grant dateNov 20, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Defect inspection methods and systems that use process conditions to dynamically determine how to perform defect inspections during a semiconductor manufacturing process are disclosed. A defect inspection method may include: obtaining process conditions from a process tool utilized to process at least one wafer; determining whether to perform defect inspection of a layer, a wafer, or a high risk area/spot within the at least one wafer based on the process conditions obtained; bypassing the defect inspection when it is determined not to perform the defect inspection; and performing the defect inspection after the at least one wafer is processed by the process tool when it is determined to perform the defect inspection.

First claim

Opening claim text (preview).

What is claimed is: 1. A wafer inspection method comprising: obtaining manufacturing process tool parameter data from a manufacturing process tool configured to process at least one wafer; determining whether to bypass a defect inspection process of the at least one wafer or perform a defect inspection process of the at least one wafer based on the obtained manufacturing process tool parameter data; and performing the defect inspection process of the at least one wafer in response to a determination to perform the defect inspection. 2. The method of claim 1 , wherein said determining whether to perform a defect inspection process is based on whether the obtained manufacturing process tool parameter data exhibits at least one anomaly. 3. The method of claim 2 , wherein the at least one wafer includes a plurality of wafers, and wherein said determining whether to perform a defect inspection process further comprises: determining whether to perform defect inspection of an entirety of the plurality of wafers or a selected subset of the plurality of wafers. 4. The method of claim 3 , wherein the selected subset of the plurality of wafers includes wafers identified to be most likely affected by the at least one anomaly, wherein the at least one anomaly is identified by obtained manufacturing process tool parameter data relating to a process condition of at least one of a gas flow, a temperature, or a pressure. 5. The method of claim 1 , wherein said performing the defect inspection process of the at least one wafer further comprises: identifying at least one of a high risk area and a high risk spot within the at least one wafer; and performing the defect inspection process of the at least one of the high risk area and the high risk spot identified. 6. The method of claim 5 , wherein said performing the defect inspection process of the at least one wafer further comprises: adjusting settings of at least one inspection device utilized to perform the defect inspection process based on the at least one of the high risk area and the high risk spot identified. 7. The method of claim 1 , wherein said performing the defect inspection process of the at least one wafer is performed prior to processing the at least one wafer utilizing another manufacturing process tool. 8. A wafer manufacturing method comprising: processing at least one wafer utilizing a manufacturing process tool; obtaining manufacturing process tool parameter data from the manufacturing process tool; determining whether to bypass a defect inspection process of the at least one wafer or perform a defect inspection process of the at least one wafer based on obtained manufacturing process tool parameter data; and performing the defect inspection process of the at least one wafer in response to a determination to perform the defect inspection. 9. The method of claim 8 , wherein said performing the defect inspection process of the at least one wafer is performed prior to processing the at least one wafer utilizing another manufacturing process tool. 10. The method of claim 8 , wherein said determining whether to perform the defect inspection process is based on whether the obtained manufacturing process tool parameter data exhibits at least one anomaly. 11. The method of claim 9 , wherein the at least one wafer includes a plurality of wafers, and wherein said determining whether to perform the defect inspection process further comprises: determining whether to perform the defect inspection process of an entirety of the plurality of wafers or a selected subset of the plurality of wafers. 12. The method of claim 11 , wherein the selected subset of the plurality of wafers includes wafers identified to be most likely affected by the at least one anomaly, wherein the at least one anomaly is identified by obtained manufacturing process tool parameter data relating to a process condition of at least one of a gas flow, a temperature, or a pressure. 13. The method of claim 8 , wherein said performing the defect inspection process of the at least one wafer further comprises: identifying at least one of a high risk area and a high risk spot within the at least one wafer; and performing the defect inspection process of the at least one of the high risk area and the high risk spot identified. 14. The method of claim 13 , wherein said performing the defect inspection process of the at least one wafer further comprises: adjusting settings of at least one inspection device utilized to perform the defect inspection process based on the at least one of the high risk area and the high risk spot identified. 15. A system comprising: a data interface, the data interface configured to obtain manufacturing process tool parameter data from a manufacturing process tool configured to process at least one wafer; a processor in communication with the data interface, the processor configured to determine whether to bypass a defect inspection process of the at least one wafer or perform a defect inspection process of the at least one wafer based on obtained manufacturing process tool parameter data; and an inspection device in communication with the processor, wherein the processor is configured to direct the inspection device to perform the defect inspection process of the at least one wafer in response to a determination to perform the defect inspection. 16. The system of claim 15 , wherein the processor determines whether to perform the defect inspection process based on whether the obtained manufacturing process tool parameter data exhibits at least one anomaly. 17. The system of claim 16 , wherein the at least one wafer includes a plurality of wafers, and wherein the processor is further configured to determine whether to perform the defect inspection process of an entirety of the plurality of wafers or a selected subset of the plurality of wafers. 18. The system of claim 17 , wherein the selected subset of the plurality of wafers includes wafers identified to be most likely affected by the at least one anomaly, wherein the at least one anomaly is identified by obtained manufacturing process tool parameter data relating to a process condition of at least one of a gas flow, a temperature, or a pressure. 19. The system of claim 15 , wherein the processor is further configured to identify at least one of a high risk area and a high risk spot within the at least one wafer and provide location information of the at least one of the high risk area and the high risk spot to the inspection device. 20. The system of claim 19 , wherein the inspection device is further configured to adjust defect inspection process settings based on the at least one of the high risk area and the high risk spot identified. 21. A wafer inspection method comprising: obtaining manufacturing process tool parameter data from a manufacturing process tool configured to process at least one wafer; determining whether to bypass a defect inspection process of the at least one wafer or perform a defect inspection process of the at least one wafer based on the obtained manufacturing process tool parameter data; and bypassing the defect inspection process of the at least one wafer in response to the determination to bypass the defect inspection. 22. A system comprising: a data interface, the data interface configured to obtain manufacturing process tool parameter data from a manufacturing process tool configured to process at least one wafer; a processor in communication

Assignees

Inventors

Classifications

  • Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

  • characterised by multiple measurements, corrections, marking or sorting processes · CPC title

  • Electricity · mapped topic

  • characterised by quality surveillance of production · CPC title

  • Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] · CPC title

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What does patent US10133263B1 cover?
Defect inspection methods and systems that use process conditions to dynamically determine how to perform defect inspections during a semiconductor manufacturing process are disclosed. A defect inspection method may include: obtaining process conditions from a process tool utilized to process at least one wafer; determining whether to perform defect inspection of a layer, a wafer, or a high ris…
Who is the assignee on this patent?
Kla Tencor Corp
What technology area does this patent fall under?
Primary CPC classification G05B19/41875. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Nov 20 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).