Nanoporous semiconductor materials and manufacture thereof

Patent metadata

Field	Value
Publication number	US-10128341-B2
Application number	US-201715462620-A
Country	US
Kind code	B2
Filing date	Mar 17, 2017
Priority date	Mar 18, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

Methods for forming nanoporous semiconductor materials are described. The methods allow for the formation of micron-scale arrays of sub-10 nm nanopores in semiconductor materials with narrow size distributions and aspect ratios of over 400:1.

First claim

What is claimed is:

1. A method for forming a nanoporous semiconductor material, the method comprising:
positioning a plurality of nanoparticles proximate a semiconductor substrate, wherein at least some of the nanoparticles of the plurality of the nanoparticles comprises a noble metal core and a sacrificial spacer layer surrounding the noble metal core;
assembling at least a portion of the nanoparticles comprising a noble metal core and a sacrificial spacer layer surrounding the noble metal core into a close-packed array;
removing at least a portion of the sacrificial spacer layer from at least some nanoparticles of the plurality of assembled nanoparticles to form a plurality of spaced noble metal nanoparticles; and
forming a plurality of pores in the semiconductor substrate by etching the semiconductor substrate at a location of at least a portion of the plurality of spaced noble metal nanoparticles.

2. The method of claim 1 , wherein the noble metal nanoparticles catalyze the etching of the semiconductor.

3. The method of claim 1 , wherein the noble metal cores of the plurality of nanoparticles have an average diameter of less than 15 nm.

4. The method of claim 1 , wherein the sacrificial spacer layers of the plurality of nanoparticles have an average thickness of less than 25 nm.

5. The method of claim 1 , wherein the semiconductor is etched with an etching solution comprising hydrofluoric acid and hydrogen peroxide.

6. The method of claim 5 , wherein the sacrificial spacer layer is removed by immersing the nanoparticles deposited on the semiconductor substrate in the etching solution.

7. The method of claim 1 , wherein the semiconductor substrate comprises silicon.

8. The method of claim 1 , wherein each noble metal core of the plurality of nanoparticles comprises gold.

9. The method of claim 1 , wherein each sacrificial spacer layer of the plurality of nanoparticles comprises SiO 2 .

10. The method of claim 1 , further comprising depositing a functional layer on the surface of each pore of the plurality of pores.

11. The method of claim 10 , wherein the functional layer is deposited by at least one of an atomic layer deposition process and a chemical vapor deposition process.

12. The method of claim 10 , wherein the functional layer comprises at least one of Al 2 O 3 and TiO 2 .

13. A nanoporous semiconductor material formed by the method of claim 1 .

14. A method comprising:
removing at least a portion of a sacrificial material from a plurality of noble-metal containing nanoparticles positioned proximate a semiconductor substrate to form an array of a plurality of spaced noble metal-containing nanoparticles proximate the substrate; and
etching the semiconductor surface proximate the array to form a nanoporous semiconductor material.

15. The method of claim 14 , comprising etching the semiconductor surface in a pattern affected by the array.

16. The method of claim 14 , wherein the plurality of noble-metal-containing nanoparticles have an average diameter of less than 15 nm.

17. The method of claim 14 , wherein the sacrificial material of the plurality of noble-metal-containing nanoparticles has an average thickness of less than 25 nm.

18. A method comprising:
forming a plurality of noble metal islands proximate a semiconductor substrate; and
forming a plurality of pores in the semiconductor substrate by etching the semiconductor surface at a location of at least a portion of the plurality of noble metal islands wherein forming the plurality of noble metal islands comprises depositing a noble metal layer on the semiconductor substrate, and wherein depositing the noble metal layer comprises a physical layer deposition process.

19. The method of claim 18 , further comprising depositing a functional layer on the surface of each pore of the plurality of pores.

20. The method of claim 19 , wherein the functional layer is deposited by at least one of an atomic layer deposition process and a chemical vapor deposition process.

21. The method of claim 19 , wherein the function layer comprises at least one of Al 2 O 3 and TiO 2 .

22. The method of claim 18 , wherein the physical vapor deposition process is at least one of magnetron sputtering, electron beam assisted deposition, and thermal evaporation.

23. The method of claim 18 , wherein the noble metal islands catalyze the etching of the semiconductor.

24. The method of claim 18 , wherein the noble metal islands have an average diameter of less than 10 nm.

25. The method of claim 18 , wherein the noble metal islands have an average spacing of less than 15 nm.

26. The method of claim 18 , wherein the semiconductor is etched with an etching solution comprising an acid and an oxidizer.

27. The method of claim 18 , wherein the semiconductor substrate comprises silicon.

28. The method of claim 18 , wherein each noble metal island comprises at least one of gold and silver.

29. A nanoporous semiconductor material formed by the method of claim 18 .

Assignees

• Massachusetts Inst Technology

Inventors

• Grossman Jeffrey C
• Smith Brendan Derek
• Patil Jatin Jayesh
• Ferralis Nicola

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/642 Primary

  Chemical etching · CPC title

• H01L29/32 Primary

  Electricity · mapped topic

• H01L21/30604

  Electricity · mapped topic

• H01L29/16

  Electricity · mapped topic