Semiconductor devices including an isolation layer on a fin and methods of forming semiconductor devices including an isolation layer on a fin

Patent metadata

Field	Value
Publication number	US-10128246-B2
Application number	US-201715616455-A
Country	US
Kind code	B2
Filing date	Jun 7, 2017
Priority date	Aug 11, 2014
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

Semiconductor devices are provided. A semiconductor device includes a fin protruding from a substrate. Moreover, the semiconductor device includes first and second gate structures on the fin, and an isolation region between the first and second gate structures. The isolation region includes first and second portions having different respective widths. Related methods of forming semiconductor devices are also provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
a fin on a substrate and extending in a first direction;
first and second transistors on the fin and spaced apart from each other in the first direction;
an isolation layer in the fin between the first and second transistors, the isolation layer extending in a second direction intersecting the first direction and isolating the first and second transistors from each other; and
spacers on at least one side of the isolation layer,
wherein the isolation layer comprises a first region on side surfaces of the spacers and a second region that overlaps upper surfaces of the spacers, and
wherein the first region comprises a narrower width, in the first direction, than the second region.

2. The semiconductor device of claim 1 ,
wherein the spacers comprise inner spacers and dummy spacers comprising different materials, respectively,
wherein the first region of the isolation layer is on side surfaces of the inner spacers and side surfaces of the dummy spacers, and
wherein the second region is on top portions of the inner spacers and the side surfaces of the dummy spacers.

3. The semiconductor device of claim 2 , wherein the first and second regions comprise a nitride layer and an oxide layer, respectively.

4. The semiconductor device of claim 1 ,
wherein the spacers comprise inner spacers and dummy spacers comprising different materials, respectively,
wherein the first region is on top portions of the inner spacers and side surfaces of the dummy spacers, and
wherein the second region is on the top portions of the inner spacers and top portions of the dummy spacers.

5. The semiconductor device of claim 4 , wherein the first and second regions comprise an oxide layer.

6. The semiconductor device of claim 1 ,
wherein the spacers comprise inner spacers and dummy spacers comprising different materials, respectively,
wherein the isolation layer further comprises a third region comprising a wider width than the second region,
wherein the first region is on side surfaces of the inner spacers,
wherein the second region is on top portions of the inner spacers and side surfaces of the dummy spacers, and
wherein the third region is on the top portions of the inner spacers and top portions of the dummy spacers.

7. The semiconductor device of claim 6 , wherein the first region comprises a nitride layer, and the second and third regions comprise an oxide layer.

8. The semiconductor device of claim 1 , wherein the spacers comprise:
inner spacers comprising an oxide layer; and
dummy spacers comprising a nitride layer.

9. The semiconductor device of claim 1 , wherein the narrower width of the first region is below the second region.

10. The semiconductor device of claim 9 ,
wherein an upper surface of the first region is above an upper surface of the fin, and
wherein an upper surface of the second region is above the upper surface of the first region.

11. The semiconductor device of claim 10 , wherein the first region protrudes upwardly from a recess region in the fin.

12. The semiconductor device of claim 1 , wherein the first region is between the second region and the substrate.

13. A semiconductor device comprising:
a fin on a substrate and extending in a first direction;
a first transistor on the fin and comprising a first spacer;
a second transistor on the fin, spaced apart from the first transistor in the first direction, and comprising a second spacer;
an isolation layer in the fin between the first and second transistors, the isolation layer extending in a second direction intersecting the first direction and isolating the first and second transistors from each other; and
dummy spacers on at least one side of the isolation layer,
wherein heights of top surfaces of the dummy spacers are shorter than heights of top surfaces of the first and second spacers.

14. The semiconductor device of claim 13 , wherein the isolation layer comprises an oxide layer and a nitride layer.

15. The semiconductor device of claim 14 , wherein the oxide layer is on a top surface of the nitride layer.

16. The semiconductor device of claim 13 ,
wherein each of the dummy spacers comprises a first region and a second region underlying the first region,
wherein the first region comprises a narrower width than the second region, and
wherein a height of a top surface of the first region is shorter than heights of the top surfaces of the first and second spacers.

17. The semiconductor device of claim 13 , further comprising a gate capping layer of the first and second transistors, wherein a top surface of the gate capping layer, the top surfaces of the first and second spacers, and a top surface of the isolation layer are substantially coplanar.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Sang-Jine
• Yoon Bo-Un
• Jeon Ha-Young
• Gil Yeon-Jin
• Yun Ji-Won
• Choi Won-Sang

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H01L21/823807

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic